B3.4 ERR0FR, Error Record Feature Register

The ERR0FR defines which of the common architecturally-defined features are implemented and, of the implemented features, which are software programmable.

Bit field descriptions

ERR0FR is a 64-bit register, and is part of the Reliability, Availability, Serviceability (RAS) registers functional group.

The register is Read Only.

Figure B3-2 ERR0FR bit assignments
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Read-as-zero/Write ignore.
CEO, [19:18]

Corrected Error Overwrite. The value is:


Counts CE if a counter is implemented and keeps the previous error status. If the counter overflows, or no counter is implemented, ERR0STATUS.OF is set to 1.

DUI, [17:16]

Error recovery interrupt for deferred errors. The value is:


The core does not support this feature.

RP, [15]

Repeat counter. The value is:


A first repeat counter and a second other counter are implemented. The repeat counter is the same size as the primary error counter.

CEC, [14:12]
Corrected Error Counter. The value is:
0b010The node implements an 8-bit standard CE counter in ERR0MISC0[39:32].
CFI, [11:10]
Fault handling interrupt for corrected errors. The value is:
0b10The node implements a control for enabling fault handling interrupts on corrected errors.
UE, [9:8]
In-band uncorrected error reporting. The value is:
0b01The node implements in-band uncorrected error reporting, that is external aborts.
FI, [7:6]
Fault handling interrupt. The value is:
0b10The node implements a fault handling interrupt and implements controls for enabling and disabling.
UI, [5:4]
Error recovery interrupt for uncorrected errors. The value is:
0b10The node implements an error recovery interrupt and implements controls for enabling and disabling.
DE, [3:2]
Defers Errors enable. The value is:
Defers Errors always enabled.
ED, [1:0]
Error detection and correction The value is:
0b10Error detection is controllable.
ERR0FR is accessible from the following registers when ERRSELR.SEL==0:
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