Chapter 2 AArch64 Register Descriptions
This chapter describes the AArch64 registers for the Cortex®-A55 core Advanced SIMD and floating-point support.
It contains the following sections:
2.1 Accessing the AArch64 feature identification registers.
2.2 AArch64 register summary.
2.3 FPCR, Floating-point Control Register.
2.4 FPSR, Floating-point Status Register.
2.5 MVFR0_EL1, Media and VFP Feature Register 0, EL1.
2.6 MVFR1_EL1, Media and VFP Feature Register 1, EL1.
2.7 MVFR2_EL1, Media and VFP Feature Register 2, EL1.
2.8 FPEXC32_EL2, Floating-point Exception Control Register, EL2.