2.1 Accessing the AArch64 feature identification registers

Software can identify the Advanced SIMD and floating-point features using the feature identification registers in the AArch64 execution state.

You can access the feature identification registers in the AArch64 execution state using the MRS instruction, for example:

        MRS <Xt>, ID_AA64PFR0_EL1 ; Read ID_AA64PFR0_EL1 into Xt
        MRS <Xt>, MVFR0_EL1       ; Read MVFR0_EL1 into Xt
        MRS <Xt>, MVFR1_EL1       ; Read MVFR1_EL1 into Xt
        MRS <Xt>, MVFR2_EL1       ; Read MVFR2_EL1 into Xt

Table 2-1 AArch64 Advanced SIMD and scalar floating-point feature identification registers

AArch64 name Description
ID_AA64PFR0_EL1 Gives additional information about implemented core features in AArch64. See the Arm® Cortex®-A55 Core Technical Reference Manual.
MVFR0_EL1 See 2.5 MVFR0_EL1, Media and VFP Feature Register 0, EL1.
MVFR1_EL1 See 2.6 MVFR1_EL1, Media and VFP Feature Register 1, EL1.
MVFR2_EL1 See 2.7 MVFR2_EL1, Media and VFP Feature Register 2, EL1.
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