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The MVFR2_EL1 describes the features provided by the AArch64 Advanced SIMD and floating-point implementation.
MVFR2_EL1 is a 32-bit register.
Indicates support for miscellaneous floating-point features.
Indicates support for miscellaneous Advanced SIMD features.
To access the MVFR2_EL1:
MRS <Xt>, MVFR2_EL1 ; Read MVFR2_EL1 into Xt
Register access is encoded as follows:
Table 2-7 MVFR2_EL1 access encoding
|EL0||EL1(NS)||EL1(S)||EL2||EL3 (SCR.NS = 1)||EL3(SCR.NS = 0)|