|Home > AArch64 Register Descriptions > FPEXC32_EL2, Floating-point Exception Control Register, EL2|
The FPEXC32_EL2 provides access to the AArch32 register FPEXC from AArch64 state only. Its value has no effect on execution in AArch64 state.
FPEXC32_EL2 is a 32-bit register.
|res0||The Cortex®-A55 core implementation does not generate asynchronous floating-point exceptions.|
Enable bit. A global enable for the Advanced SIMD and floating-point support:
|The Advanced SIMD and floating-point support is disabled. This is the reset value.|
|The Advanced SIMD and floating-point support is enabled and operates normally.|
This bit applies only to AArch32 execution, and only when EL1 is not AArch64.
To access the FPEXC32_EL2:
MRS <Xt>, FPEXC32_EL2 ; Read FPEXC32_EL2 into Xt MSR FPEXC32_EL2, <Xt> ; Write Xt to FPEXC32_EL2
Register access is encoded as follows:
Table 2-8 FPEXC32_EL2 access encoding
(SCR.NS = 1)
(SCR.NS = 0)