3.2 AArch32 register summary

The following table gives a summary of the Cortex®-A55 core Advanced SIMD and floating-point system registers in the AArch32 execution state.

Table 3-2 AArch32 Advanced SIMD and floating-point system registers

Name Type Reset Description
FPSID RO 0x41034052 See 3.3 FPSID, Floating-Point System ID Register.
FPSCR RW 0x00000000 See 3.4 FPSCR, Floating-Point Status and Control Register.
MVFR0 RO 0x10110222 See 3.5 MVFR0, Media and VFP Feature Register 0.
MVFR1 RO 0x13211111 See 3.6 MVFR1, Media and VFP Feature Register 1.
MVFR2 RO 0x00000043 See 3.7  MVFR2, Media and VFP Feature Register 2.
FPEXC RW 0x00000700 See 3.8 FPEXC, Floating-Point Exception Control register.

Note:

The Floating-Point Instruction Registers, FPINST and FPINST2 are not implemented, and any attempt to access them is unpredictable.

See the Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile for information on permitted accesses to the Advanced SIMD and floating-point system registers.

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