Arm® DynamIQ™ Shared Unit Technical Reference Manual

Revision r4p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Typographic conventions
Timing diagrams
Additional reading
Feedback on this product
Feedback on content
Part A Functional Description
A1 Introduction
A1.1 About the DSU
A1.2 Features
A1.3 Implementation options
A1.3.1 Cluster configurations
A1.4 Supported standards and specifications
A1.5 Test features
A1.6 Design tasks
A1.7 Product revisions
A2 Technical overview
A2.1 Components
A2.2 Interfaces
A2.3 RAS support
A2.4 Page Based Hardware Attribute
A2.5 L3 memory system variants
A3 Clocks and resets
A3.1 Clocks
A3.2 Resets
A4 Power management
A4.1 About DSU power management
A4.2 Power mode control
A4.3 Communication with the power controller
A4.4 L3 RAM power control
A4.4.1 L3 cache partial powerdown
A4.4.2 L3 RAM retention
A4.5 Power modes
A4.5.1 Power mode transitions
A4.5.2 Power mode transition behavior
A4.5.3 Interlocks between core and DSU P-Channels
A4.5.4 Power mode encoding
A4.6 Power operating requirements
A4.6.1 Power control for DFT
A4.7 Wait For Interrupt and Wait For Event
A4.8 Clock, voltage, and power domains
A4.9 Cluster powerdown
A4.9.1 Transitioning in and out of coherency
A5 L3 cache
A5.1 About the L3 cache
A5.2 L3 cache allocation policy
A5.3 L3 cache partitioning
A5.4 Cache stashing
A5.5 L3 cache ECC and parity
A5.6 L3 cache data RAM latency
A5.7 Cache slices and portions
A5.7.1 Cache slice and master port selection
A5.7.2 1.5MB or 3MB L3 cache implementation
A5.7.3 Default number of cache slices
A6 ACE master interface
A6.1 About the ACE master interface
A6.1.1 Dual ACE interfaces
A6.2 ACE configurations
A6.3 ACE features
A6.4 ACE master interface attributes
A6.5 ACE channel properties
A6.6 ACE transactions
A6.7 Support for memory types
A6.8 Read response
A6.9 Write response
A6.10 Barriers
A6.11 AXI compatibility mode
A6.11.1 Additional logic to support AXI compatibility
A6.12 ACE privilege information
A7 CHI master interface
A7.1 About the CHI master interface
A7.1.1 Dual CHI interfaces
A7.2 CHI version
A7.3 CHI features
A7.4 CHI configurations
A7.5 Attributes of the CHI master interface
A7.6 CHI channel properties
A7.7 CHI transactions
A7.8 Use of DataSource
A7.9 Support for memory types
A8 ACP slave interface
A8.1 About the ACP
A8.2 ACP features
A8.3 ACP ACE-Lite subset
A8.4 ACP transaction types
A8.5 ACP performance
A9 AXI master peripheral port
A9.1 About the peripheral port
A9.2 Transaction ID encoding
Part B Register Descriptions
B1 Control registers
B1.1 About the control registers
B1.2 AArch32 control register summary
B1.3 AArch64 control register summary
B1.4 CLUSTERACPSID, Cluster ACP Scheme ID Register
B1.5 CLUSTERACTLR, Cluster Auxiliary Control Register
B1.6 CLUSTERBUSQOS, Cluster Bus QoS Control Register
B1.7 CLUSTERCFR, Cluster Configuration Register
B1.8 CLUSTERECTLR, Cluster Extended Control Register
B1.9 CLUSTERIDR, Cluster Main Revision ID Register
B1.10 CLUSTERL3HIT, Cluster L3 Hit Counter Register
B1.11 CLUSTERL3MISS, Cluster L3 Miss Counter Register
B1.12 CLUSTERPARTCR, Cluster Partition Control Register
B1.13 CLUSTERPWRCTLR, Cluster Power Control Register
B1.14 CLUSTERPWRDN, Cluster Powerdown Register
B1.15 CLUSTERPWRSTAT, Cluster Power Status Register
B1.16 CLUSTERREVIDR, Cluster Revision ID Register
B1.17 CLUSTERSTASHSID, Cluster Stash Scheme ID Register
B1.18 CLUSTERTHREADSID, Cluster Thread Scheme ID Register
B1.19 CLUSTERTHREADSIDOVR, Cluster Thread Scheme ID Override Register
B2 Error system registers
B2.1 About the error system registers
B2.2 Error system register summary
B2.3 ERR1CTLR, Error Record Control Register
B2.4 ERR1FR, Error Record Feature Register
B2.5 ERR1MISC0, Error Record Miscellaneous Register 0
B2.6 ERR1MISC1, Error Record Miscellaneous Register 1
B2.7 ERR1PFGCDNR, Error Pseudo Fault Generation Count Down Register
B2.8 ERR1PFGCTLR, Error Pseudo Fault Generation Control Register
B2.9 ERR1PFGFR, Error Pseudo Fault Generation Feature Register
B2.10 ERR1STATUS, Error Record Primary Status Register
B3 PMU registers
B3.1 About the PMU registers
B3.2 AArch32 PMU register summary
B3.3 AArch64 PMU register summary
B3.4 CLUSTERPMCR, Cluster Performance Monitors Control Register
B3.5 CLUSTERPMCNTENSET, Cluster Count Enable Set Register
B3.6 CLUSTERPMCNTENCLR, Cluster Count Enable Clear Register
B3.7 CLUSTERPMOVSSET, Cluster Overflow Flag Status Set Register
B3.8 CLUSTERPMOVSCLR, Cluster Overflow Flag Status Clear Register
B3.9 CLUSTERPMSELR, Cluster Event Counter Selection Register
B3.10 CLUSTERPMINTENSET, Cluster Interrupt Enable Set Register
B3.11 CLUSTERPMINTENCLR, Cluster Interrupt Enable Clear Register
B3.12 CLUSTERPMCCNTR, Cluster Performance Monitors Cycle Counter
B3.13 CLUSTERPMXEVTYPER, Cluster Selected Event Type Register
B3.14 CLUSTERPMXEVCNTR, Cluster Selected Event Counter Register
B3.15 CLUSTERPMMDCR, Cluster Monitor Debug Configuration Register
B3.16 CLUSTERPMCEID0, Cluster Common Event Identification Register 0
B3.17 CLUSTERPMCEID1, Cluster Common Event Identification Register 1
B3.18 CLUSTERCLAIMSET, Cluster Claim Tag Set Register
B3.19 CLUSTERCLAIMCLR, Cluster Claim Tag Clear Register
B3.20 CLUSTERPMEVTYPER<n>, Cluster Event Type Register
B3.21 CLUSTERPMEVCNTR<n>, Cluster Event Counter Register
Part C Debug
C1 Debug
C1.1 About debug methods
C1.2 Terminology
C1.3 About the DebugBlock
C1.4 DebugBlock components
C1.5 About the Embedded Cross Trigger
C1.5.1 Supported debug and trace trigger events
C1.6 CTI triggers
C2.1 About the PMU
C2.2 PMU functional description
C2.3 PMU events
C2.4 PMU interrupts
C3 Debug registers
C3.1 Debug memory map
C3.2 CTI register summary
C3.3 CTIPIDR0, CTI Peripheral Identification Register 0
C3.4 CTIPIDR1, CTI Peripheral Identification Register 1
C3.5 CTIPIDR2, CTI Peripheral Identification Register 2
C3.6 CTIPIDR3, CTI Peripheral Identification Register 3
C3.7 CTIPIDR4, CTI Peripheral Identification Register 4
C3.8 CTIITCTRL, CTI Integration Mode Control Register
C3.9 CTIDEVAFF0, Cluster CTI Device Affinity register 0
C3.10 CTIDEVID, CTI Device Identification Register
C3.11 External register access permissions
C4 ROM table
C4.1 About the ROM table
C4.2 ROM table register summary
Part D Appendices
A Compatible Core Versions
A.1 Compatible Core Versions
B Signal descriptions
B.1 Signal naming convention
B.2 DSU signals
B.2.1 Clock and clock enable signals
B.2.2 Reset signals
B.2.3 Configuration signals
B.2.4 GIC signals
B.2.5 Generic Timer signals
B.2.6 Power management signals
B.2.7 Error signals
B.2.8 ACP interface signals
B.2.9 Peripheral port interface signals
B.2.10 Broadcast signals for the memory interface
B.2.11 ACE interface signals
B.2.12 CHI interface signals
B.2.13 DebugBlock APB interface signals
B.2.14 ATB interface signals
B.2.15 Timestamp signal
B.2.16 PMU interface signals
B.2.17 ELA signal
B.2.18 DFT interface signals
B.2.19 MBIST interface signals
B.3 DebugBlock signals
B.3.1 Clock signal
B.3.2 Reset signal
B.3.3 Power and clock gate control signals
B.3.4 Configuration signals
B.3.5 Debug signals
B.3.6 CTI interface signals
B.3.7 DFT signals
C Revisions
C.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 30 September 2016 Confidential First release for r0p0
0001-00 16 December 2016 Confidential First release for r0p1
0002-00 20 June 2017 Non-Confidential First release for r0p2
0100-00 31 May 2017 Confidential First release for r1p0
0200-00 16 October 2017 Confidential First release for r2p0
0300-00 26 January 2018 Non-Confidential First release for r3p0
0300-01 27 April 2018 Non-Confidential Second release for r3p0
0400-00 27 November 2018 Non-Confidential First release for r4p0
0400-01 07 December 2018 Non-Confidential Second release for r4p0

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