ARM® Cortex®‑A9 MPCore Technical Reference Manual

Revision r4p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex-A9 MPCore processor
1.1.1 Processor components
1.1.2 Example configuration
1.2 Compliance
1.2.1 ARM architecture
1.2.2 Advanced Microcontroller Bus Architecture
1.2.3 Program Flow Trace architecture
1.2.4 Debug architecture
1.2.5 Generic Interrupt Controller architecture
1.3 Configurable options
1.4 Test features
1.5 Private Memory Region
1.6 Interfaces
1.6.1 AMBA AXI interfaces
1.6.2 Interrupts interface
1.6.3 Debug interfaces
1.6.4 Design for Test interface
1.7 MPCore considerations
1.7.1 About Cortex-A9 MPCore coherency
1.7.2 Registers with multiprocessor uses
1.7.3 Maintenance operations broadcasting
1.8 Product documentation and design flow
1.8.1 Documentation
1.8.2 Design flow
1.9 Product revisions
2 Snoop Control Unit
2.1 About the SCU
2.1.1 TrustZone® extensions
2.1.2 SCU event monitoring
2.2 SCU registers
2.2.1 SCU register summary
2.2.2 SCU Control Register
2.2.3 SCU Configuration Register
2.2.4 SCU CPU Power Status Register
2.2.5 SCU Invalidate All Registers in Secure State Register
2.2.6 Filtering Start Address Register
2.2.7 Filtering End Address Register
2.2.8 SCU Access Control Register (SAC)
2.2.9 SCU Non-secure Access Control Register
2.3 AMBA AXI Master Port Interfaces
2.3.1 AXI issuing capabilities
2.3.2 Cortex-A9 MPCore AXI transactions
2.3.3 AXI transaction IDs
2.3.4 AXI USER attributes encodings
2.3.5 Address filtering capabilities
2.3.6 Device accesses filtering
2.3.7 AXI master interface clocking
2.4 Accelerator Coherency Port
2.4.1 ACP requests
2.4.2 ACP interface clocking
2.4.3 ACP limitations
2.5 Event communication with an external agent using WFE/SEV
3 Interrupt Controller
3.1 About the Interrupt Controller
3.1.1 Interrupt Controller Clock frequency
3.1.2 Interrupt Distributor interrupt sources
3.1.3 Interrupt Distributor arbitration
3.1.4 Cortex-A9 MPCore 1-N interrupt model handling
3.2 Security extensions support
3.2.1 Priority formats
3.2.2 Using CFGSDISABLE
3.3 Distributor register descriptions
3.3.1 Distributor register summary
3.3.2 Distributor Control Register
3.3.3 Interrupt Controller Type Register
3.3.4 Distributor Implementer Identification Register
3.3.5 Interrupt Set-Enable Registers
3.3.6 Interrupt Clear-Enable Registers
3.3.7 Interrupt Processor Targets Registers
3.3.8 Interrupt Configuration Registers
3.3.9 PPI Status Register
3.3.10 SPI Status Registers
3.4 Interrupt interface register descriptions
3.4.1 Processor interface register summary
3.4.2 CPU Interface Implementer Identification Register
4 Global timer, private timers, and watchdog registers
4.1 About the private timer and watchdog blocks
4.1.1 Calculating timer intervals
4.1.2 Security extensions
4.2 Private timer and watchdog registers
4.2.1 Private timer and watchdog register summary
4.2.2 Private Timer Load Register
4.2.3 Private Timer Counter Register
4.2.4 Private Timer Control Register
4.2.5 Private Timer Interrupt Status Register
4.2.6 Watchdog Load Register
4.2.7 Watchdog Counter Register
4.2.8 Watchdog Control Register
4.2.9 Watchdog Interrupt Status Register
4.2.10 Watchdog Reset Status Register
4.2.11 Watchdog Disable Register
4.3 About the Global Timer
4.4 Global timer registers
4.4.1 Global timer register summary
4.4.2 Global Timer Counter Registers, 0x00 and 0x04
4.4.3 Global Timer Control Register
4.4.4 Global Timer Interrupt Status Register
4.4.5 Comparator Value Registers, 0x10 and 0x14
4.4.6 Auto-increment Register, 0x18
5 Clocks, Resets, and Power Management
5.1 Clocks
5.2 Resets
5.2.1 Reset combinations
5.2.2 Cortex-A9 MPCore power-on reset
5.2.3 Cortex-A9 MPCore software reset
5.2.4 Individual processor power-on reset
5.2.5 Individual processor software reset
5.2.6 Individual processor power-on SIMD MPE reset
5.2.7 Cortex-A9 MPCore debug reset
5.2.8 Individual processor debug reset
5.2.9 Individual processor watchdog flag reset
5.3 Power management
5.3.1 Individual Cortex-A9 processor power management
5.3.2 Communication to the Power Management Controller
5.3.3 Cortex-A9 MPCore power domains
5.3.4 About multiprocessor bring-up
6 Debug
6.1 External Debug Interface signals
6.2 Cortex-A9 MPCore APB Debug interface and memory map
6.2.1 PADDRDBG values
6.2.2 Configuration for a single Cortex-A9 processor
6.2.3 Configuration for two Cortex-A9 processors
6.2.4 Configuration for three Cortex-A9 processors
6.2.5 Configuration for four Cortex-A9 processors
A Signal Descriptions
A.1 Clock and clock control signals
A.2 Resets and reset control signals
A.2.1 Reset signals
A.2.2 Reset clock control signals
A.2.3 Watchdog request reset signal
A.3 Interrupts
A.4 Configuration signals
A.5 Security control signals
A.6 WFE and WFI Standby signals
A.7 Power management signals
A.8 AXI interfaces
A.8.1 AXI Master0 signals
A.8.2 AXI Master1 signals
A.8.3 AXI ACP signals
A.9 Performance monitoring signals
A.10 Exception flags signals
A.11 Parity error signals
A.12 MBIST interface
A.12.1 MBIST interface signals
A.12.2 MBIST interface signals with parity support
A.12.3 MBIST interface signals without parity
A.13 Scan test signal
A.14 External Debug interface
A.14.1 Authentication interface
A.14.2 APB interface signals
A.14.3 Cross trigger interface signals
A.14.4 Miscellaneous debug interface signals
A.15 PTM interface signals
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
A 04 April 2008 Non-Confidential First release for r0p0
B 08 July 2008 Non-Confidential First release for r0p1
C 16 December 2008 Non-Confidential First release for r1p0
D 02 October 2009 Non-Confidential First release for r2p0
E 27 November 2009 Non-Confidential Second release for r2p0
F 30 April 2010 Non-Confidential First release for r2p2
G 19 July 2011 Non-Confidential First release for r3p0
H 23 March 2012 Non-Confidential First release for r4p0
I 15 June 2012 Non-Confidential First release for r4p1
0401-10 06 January 2016 Non-Confidential Converted to DITA. Document number is changed to 100486. Second release for r4p1.

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