ARM® Cortex®‑A9 Technical Reference Manual

Revision r4p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the Cortex®‑A9 processor
1.1.1 Data engine
1.1.2 System design components
1.2 Processor variants
1.3 Compliance
1.3.1 ARM® architecture
1.3.2 Advanced Microcontroller Bus Architecture
1.3.3 Program Flow Trace architecture
1.3.4 Debug architecture
1.3.5 Generic Interrupt Controller architecture
1.4 Features
1.5 Interfaces
1.6 Configurable options
1.7 Test features
1.8 Product documentation and design flow
1.8.1 Documentation
1.8.2 Design flow
1.9 Product revisions
2 Functional Description
2.1 About the functions
2.1.1 Instruction queue
2.1.2 Dynamic branch prediction
2.1.3 Register renaming
2.1.4 PTM interface
2.1.5 Performance monitoring
2.1.6 Virtualization of interrupts
2.2 Interfaces
2.2.1 AXI interface
2.2.2 APB external debug interface
2.2.3 Program Flow Trace and Program Trace Macrocell
2.3 Clocking and resets
2.3.1 Synchronous clocking
2.3.2 Reset
2.3.3 Dynamic high-level clock gating
2.4 Power management
2.4.1 Energy efficiency features
2.4.2 Processor power control
2.4.3 Power domains
2.4.4 Cortex®‑A9 voltage domains
2.5 Constraints and limitations of use
3 Programmers Model
3.1 About the programmers model
3.2 ThumbEE architecture
3.3 The Jazelle® Extension
3.4 Advanced SIMD architecture
3.5 Security Extensions architecture
3.5.1 System boot sequence
3.6 Multiprocessing Extensions
3.7 Modes of operation and execution
3.8 Memory model
3.9 Addresses in the Cortex®‑A9 processor
4 System Control
4.1 About system control
4.1.1 Deprecated registers
4.2 Register summary
4.2.1 CP15 system control registers grouped by CRn order
4.2.2 CP15 system control registers grouped by function
4.3 Register descriptions
4.3.1 Main ID Register
4.3.2 TLB Type Register
4.3.3 Multiprocessor Affinity Register
4.3.4 Revision ID register
4.3.5 Cache Size Identification Register
4.3.6 Cache Level ID Register
4.3.7 Auxiliary ID Register
4.3.8 Cache Size Selection Register
4.3.9 System Control Register
4.3.10 Auxiliary Control Register
4.3.11 Coprocessor Access Control Register
4.3.12 Secure Debug Enable Register
4.3.13 Non-secure Access Control Register
4.3.14 Virtualization Control Register
4.3.15 Data Fault Status Register
4.3.16 TLB Lockdown Register
4.3.17 PLE ID Register
4.3.18 PLE Activity Status Register
4.3.19 PLE FIFO Status Register
4.3.20 Preload Engine User Accessibility Register
4.3.21 Preload Engine Parameters Control Register
4.3.22 Virtualization Interrupt Register
4.3.23 Power Control Register
4.3.24 NEON™ Busy Register
4.3.25 Configuration Base Address Register
4.3.26 TLB lockdown operations
5 Jazelle® DBX registers
5.1 About coprocessor CP14
5.2 CP14 Jazelle® register summary
5.3 CP14 Jazelle® register descriptions
5.3.1 Jazelle® ID Register
5.3.2 Jazelle® Operating System Control Register
5.3.3 Jazelle® Main Configuration Register
5.3.4 Jazelle® Parameters Register
5.3.5 Jazelle® Configurable Opcode Translation Table Register
6 Memory Management Unit
6.1 About the MMU
6.1.1 Memory Management Unit
6.2 TLB Organization
6.2.1 Micro TLB
6.2.2 Main TLB
6.3 Memory access sequence
6.4 MMU enabling or disabling
6.5 External aborts
6.5.1 External aborts on data read or write
6.5.2 Synchronous and asynchronous aborts
7 Level 1 Memory System
7.1 About the L1 memory system
7.1.1 Memory system
7.2 Security Extensions support
7.3 About the L1 instruction side memory system
7.3.1 Enabling program flow prediction
7.3.2 Program flow prediction
7.4 About the L1 data side memory system
7.4.1 Local Monitor
7.4.2 External aborts handling
7.4.3 Cortex®‑A9 behavior for Normal Memory Cacheable memory regions
7.5 About DSB
7.6 Data prefetching
7.6.1 The PLD instruction
7.6.2 Data prefetching
7.7 Parity error support
7.7.1 GHB and BTAC data corruption
8 Level 2 Memory Interface
8.1 About the Cortex®‑A9 L2 interface
8.1.1 AXI master 0 interface and AXI master 1 interface attributes
8.1.2 Supported AXI transfers
8.1.3 AXI transaction IDs
8.1.4 AXI USER bits
8.1.5 Exclusive L2 cache
8.2 Optimized accesses to the L2 memory interface
8.2.1 Prefetch hint to the L2 memory interface
8.2.2 Early BRESP
8.2.3 Write full line of zeros
8.2.4 Speculative coherent requests
8.3 STRT instructions
9 Preload Engine
9.1 About the Preload Engine
9.2 PLE control register descriptions
9.3 PLE operations
9.3.1 Preload Engine FIFO flush operation
9.3.2 Preload Engine pause channel operation
9.3.3 Preload Engine resume channel operation
9.3.4 Preload Engine kill channel operation
9.3.5 PLE Program New Channel operation
10 Debug
10.1 Debug Systems
10.1.1 Debug host
10.1.2 Protocol converter
10.1.3 Debug target
10.2 About the Cortex®‑A9 debug interface
10.3 Debug register features
10.3.1 Processor interfaces
10.3.2 Breakpoints and watchpoints
10.3.3 Effects of resets on debug registers
10.4 Debug register summary
10.5 Debug register descriptions
10.5.1 Breakpoint Value Registers
10.5.2 Breakpoint Control Registers
10.5.3 Watchpoint Value Registers
10.5.4 Watchpoint Control Registers
10.6 Debug management registers
10.6.1 Peripheral Identification Registers
10.6.2 Component Identification Registers
10.7 Debug events
10.7.1 Watchpoints
10.7.2 Asynchronous aborts
10.8 External debug interface
10.8.1 Debugging modes
10.8.2 Authentication signals
10.8.3 Changing the authentication signals
10.8.4 Debug APB Interface
10.8.5 External debug request interface
11 Performance Monitoring Unit
11.1 About the Performance Monitoring Unit
11.2 PMU register summary
11.3 PMU management registers
11.3.1 Peripheral Identification Registers
11.3.2 Component Identification Registers
11.4 Performance monitoring events
11.4.1 Implemented architectural events
11.4.2 Cortex®‑A9 specific events
A Signal Descriptions
A.1 Clock signals
A.2 Reset signals
A.3 Interrupt line signals
A.4 Configuration signals
A.5 WFE and WFI standby signals table
A.6 Power management signals
A.7 AXI interfaces
A.7.1 AXI Master0 signals data accesses
A.7.2 AXI Master1 signals instruction accesses
A.8 Performance monitoring signals
A.8.1 Event signals and event numbers
A.9 Exception flags signal
A.10 Parity signal
A.11 MBIST interface
A.11.1 MBIST interface signals
A.11.2 MBIST signals with parity support implemented
A.11.3 MBIST signals without parity support implemented
A.12 Scan test signal
A.13 External Debug interface signals
A.13.1 Authentication interface
A.13.2 APB interface signals
A.13.3 CTI signals
A.13.4 Miscellaneous debug interface signals
A.14 PTM interface signals
B Cycle Timings and Interlock Behavior
B.1 About instruction cycle timing
B.2 Data-processing instructions
B.3 Load and store instructions
B.3.1 Single load and store operation cycle timings
B.3.2 Load multiple operations cycle timings
B.3.3 Store multiple operations cycle timings
B.4 Multiplication instructions
B.5 Branch instructions
B.6 Serializing instructions
C Revisions
C.1 Revisions

List of Figures

1 Key to timing diagram conventions
1-1 Cortex‑A9 uniprocessor system
2-1 Cortex‑A9 processor top-level diagram
2-2 PTM interface signals
2-3 ACLKENM0 used with a 3:1 clock ratio
2-4 Power domains for the Cortex‑A9 processor
4-1 MIDR bit assignments
4-2 TLBTR bit assignments
4-3 MPIDR bit assignments
4-4 REVIDR bit assignments
4-5 CCSIDR bit assignments
4-6 CLIDR bit assignments
4-7 CSSELR bit assignments
4-8 SCTLR bit assignments
4-9 ACTLR bit assignments
4-10 CPACR bit assignments
4-11 SDER bit assignments
4-12 NSACR bit assignments
4-13 VCR bit assignments
4-14 DFSR bit assignments
4-15 TLB Lockdown Register bit assignments
4-16 PLEIDR bit assignments
4-17 PLEASR bit assignments
4-18 PLESFR bit assignments
4-19 PLEUAR bit assignments
4-20 PLEPCR bit assignments
4-21 VIR bit assignments
4-22 Power Control Register bit assignments
4-23 NEON Busy Register bit assignments
4-24 Configuration Base Address Register bit assignments
4-25 Lockdown TLB index bit assignments
4-26 TLB VA Register bit assignments
4-27 Memory space identifier format
4-28 TLB PA Register bit assignments
4-29 Main TLB Attributes Register bit assignments
5-1 JIDR bit assignments
5-2 JOSCR bit assignments
5-3 JMCR bit assignments
5-4 Jazelle Parameters Register bit assignments
5-5 Jazelle Configurable Opcode Translation Table Register bit assignments
7-1 Branch prediction and instruction cache
7-2 Parity support
9-1 Program new channel operation bit assignments
10-1 Typical debug system
10-2 Debug registers interface and CoreSight infrastructure
10-3 BCR Register bit assignments
10-4 WCR Register bit assignments
10-5 External debug interface signals
10-6 Debug request restart-specific connections

List of Tables

1-1 Configurable options for the Cortex‑A9 processor
2-1 Reset modes
2-2 Cortex‑A9 processor power modes
3-1 CPSR J and T bit encoding
3-2 Address types in the processor system
4-1 Column headings definition for CP15 register summary tables
4-2 c0 register summary
4-3 c1 register summary
4-4 c2 register summary
4-5 c3 register summary
4-6 c5 register summary
4-7 c6 register summary
4-8 c7 register summary
4-9 c8 register summary
4-10 c9 register summary
4-11 c10 register summary
4-12 c11 register summary
4-13 c12 register summary
4-14 c13 register summary
4-15 c15 system control register summary
4-16 Processor ID registers
4-17 Virtual memory registers
4-18 Fault handling registers
4-19 Other system control registers
4-20 Cache and branch predictor maintenance operations
4-21 Address translation operations
4-22 Miscellaneous system control operations
4-23 Performance monitor registers
4-24 Security Extensions registers
4-25 Preload engine registers
4-26 TLB maintenance
4-27 Implementation defined registers
4-28 MIDR bit assignments
4-29 TLBTR bit assignments
4-30 MPIDR bit assignments
4-31 REVIDR bit assignments
4-32 CCSIDR bit assignments
4-33 CLIDR bit assignments
4-34 CSSELR bit assignments
4-35 SCTLR bit assignments
4-36 ACTLR bit assignments
4-37 CPACR bit assignments
4-38 SDER bit assignments
4-39 NSACR bit assignments
4-40 VCR bit assignments
4-41 DFSR bit assignments
4-42 TLB Lockdown Register bit assignments
4-43 PLEIDR bit assignments
4-44 PLEASR bit assignments
4-45 PLESFR bit assignments
4-46 PLEUAR bit assignments
4-47 PLEPCR bit assignments
4-48 Virtualization Interrupt Register bit assignments
4-49 Power Control Register bit assignments
4-50 NEON Busy Register bit assignments
4-51 TLB lockdown operations
4-52 TLB VA Register bit assignments
4-53 TLB PA Register bit assignments
4-54 TLB Attributes Register bit assignments
5-1 CP14 Jazelle registers summary
5-2 JIDR bit assignments
5-3 JOSCR bit assignments
5-4 JMCR bit assignments
5-5 Jazelle Parameters Register bit assignments
5-6 Jazelle Configurable Opcode Translation Table Register bit assignments
7-1 Effect of implementation defined instructions and write operations
8-1 AXI master 0 interface attributes
8-2 AXI master 1 interface attributes
8-3 ARUSERM0[6:0] encodings
8-4 ARUSERM1[6:0] encodings
8-5 AWUSERM0[8:0] encodings
8-6 Cortex‑A9 mode and AxPROT values
9-1 PLE program new channel operation bit assignments
10-1 CP14 debug register summary
10-2 BVRs and corresponding BCRs
10-3 Breakpoint Value Registers bit functions
10-4 BCR Register bit assignments
10-5 Meaning of BVR as specified by BCR bits [22:20]
10-6 WVRs and corresponding WCRs
10-7 Watchpoint Value Registers bit functions
10-8 WCR Register bit assignments
10-9 Debug management registers
10-10 Peripheral Identification Register Summary
10-11 Component Identification Register Summary
10-12 Authentication signal restrictions
11-1 PMU register summary
11-2 PMU management registers
11-3 Peripheral Identification Registers
11-4 Component Identification Registers
11-5 Implemented architectural events
11-6 Cortex‑A9 specific events
A-1 Clock and clock control signals
A-2 Reset signals
A-3 Interrupt line signals
A-4 Configuration signals
A-5 CP15SDISABLE signal
A-6 WFE and WFI standby signals
A-7 Power management signals
A-8 Write address channel signals for AXI Master0
A-9 AXI-W signals for AXI Master0
A-10 Write response channel signals for AXI Master0
A-11 Read address channel signals for AXI Master0
A-12 Read data channel signals for AXI Master0
A-13 Clock enable signal for AXI Master0
A-14 Read address channel signals for AXI Master1
A-15 AXI-R signals for AXI Master1
A-16 Clock enable signal for AXI Master1
A-17 Performance monitoring signals
A-18 Event signals and event numbers
A-19 DEFLAGS signal
A-20 Parity signal
A-21 MBIST interface signals
A-22 MBIST signals with parity support implemented
A-23 MBIST signals without parity support implemented
A-24 Scan test signal
A-25 Authentication interface signals
A-26 APB interface signals
A-27 CTI signals
A-28 Miscellaneous debug signals
A-29 PTM interface signals
B-1 Data-processing instructions cycle timings
B-2 Single load and store operation cycle timings
B-3 Load multiple operations cycle timings
B-4 Store multiple operations cycle timings
B-5 Multiplication instruction cycle timings
C-1 Issue A
C-2 Differences between issue A and issue B
C-3 Differences between issue B and issue C
C-4 Differences between issue C and issue D
C-5 Differences between issue D and issue F
C-6 Differences between issue F and issue G
C-7 Differences between issue G and issue H
C-8 Differences between issue H and issue I
C-9 Differences between issue I and issue 10

Release Information

Document History
Issue Date Confidentiality Change
A 31 March 2008 Non-Confidential First release for r0p0
B 08 July 2008 Non-Confidential First release for r0p1
C 17 December 2008 Non-Confidential First release for r1p0
D 30 September 2009 Non-Confidential First release for r2p0
E 27 November 2009 Non-Confidential Second release for r2p0
F 30 April 2010 Non-Confidential First release for r2p2
G 19 July 2011 Non-Confidential First release for r3p0
H 22 March 2012 Non-Confidential First release for r4p0
I 15 June 2012 Non-Confidential First release for r4p1
0401-10 11 February 2016 Non-Confidential Source content converted to DITA. Document number changed to 100511. Second release for r4p1.

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