ARM® CoreSight™ SoC-400 Technical Reference Manual

Revision r3p2


Table of Contents

Preface
About this book
Product Revision Status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 About CoreSight™ SoC-400
1.1 About CoreSight™ SoC-400
1.1.1 Structure of CoreSight™ SoC-400
1.1.2 CoreSight™ SoC-400 block summary
1.1.3 Typical CoreSight™ SoC-400 system
1.2 Compliance
1.3 Features
1.4 Interfaces
1.5 Configurable options
1.6 Test features
1.7 Product documentation and design flow
1.8 Product revisions
2 Functional Overview
2.1 DAP components
2.1.1 Serial Wire or JTAG Debug Port
2.1.2 DAPBUS interconnect
2.1.3 DAPBUS asynchronous bridge
2.1.4 DAPBUS synchronous bridge
2.1.5 JTAG access port
2.1.6 AXI access port
2.1.7 AHB access port
2.1.8 APB access port
2.2 APB components
2.2.1 APB interconnect with ROM table
2.2.2 APB asynchronous bridge
2.2.3 APB synchronous bridge
2.3 ATB interconnect components
2.3.1 ATB replicator
2.3.2 ATB funnel
2.3.3 ATB upsizer
2.3.4 ATB downsizer
2.3.5 ATB asynchronous bridge
2.3.6 ATB synchronous bridge
2.3.7 ATB phantom bridges
2.4 Timestamp components
2.4.1 Timestamp generator
2.4.2 Timestamp encoder
2.4.3 Narrow timestamp replicator
2.4.4 Narrow timestamp asynchronous bridge
2.4.5 Narrow timestamp synchronous bridge
2.4.6 Timestamp decoder
2.4.7 Timestamp interpolator
2.5 Embedded Cross Trigger components
2.5.1 Cross Trigger Interface
2.5.2 Cross Trigger Matrix
2.5.3 Event asynchronous bridge
2.5.4 Channel asynchronous bridge
2.5.5 Cross Trigger to System Trace Macrocell
2.6 Trace sink components
2.6.1 Trace Port Interface Unit
2.6.2 Embedded Trace Buffer
2.7 Authentication bridges
2.7.1 Authentication replicator
2.7.2 Authentication asynchronous bridge
2.7.3 Authentication synchronous bridge
2.8 Granular Power Requester
3 About the programmers model
3.1 About the programmers model
3.2 Granular Power Requester registers
3.2.1 Granular Power Requester register summary
3.2.2 Debug Power Request register, CPWRUPREQ
3.2.3 Debug Power Acknowledge register, CPWRUPACK
3.2.4 Integration Mode Control register, ITCTRL
3.2.5 Claim Tag Set register, CLAIMSET
3.2.6 Claim Tag Clear register, CLAIMCLR
3.2.7 Lock Access Register, LAR
3.2.8 Lock Status Register, LSR
3.2.9 Authentication Status register, AUTHSTATUS
3.2.10 Device Architecture register, DEVARCH
3.2.11 Device Configuration register, DEVID
3.2.12 Device Type Identifier register, DEVTYPE
3.2.13 Peripheral ID0 Register, PIDR0
3.2.14 Peripheral ID1 Register, PIDR1
3.2.15 Peripheral ID2 Register, PIDR2
3.2.16 Peripheral ID3 Register, PIDR3
3.2.17 Peripheral ID4 Register, PIDR4
3.2.18 Component ID0 Register, CIDR0
3.2.19 Component ID1 Register, CIDR1
3.2.20 Component ID2 Register, CIDR2
3.2.21 Component ID3 Register, CIDR3
3.3 APB interconnect registers
3.3.1 APB interconnect register summary
3.3.2 ROM Table Entry
3.3.3 Peripheral ID4 Register, PIDR4
3.3.4 Peripheral ID0 Register, PIDR0
3.3.5 Peripheral ID1 Register, PIDR1
3.3.6 Peripheral ID2 Register, PIDR2
3.3.7 Peripheral ID3 Register, PIDR3
3.3.8 Component ID0 Register, CIDR0
3.3.9 Component ID1 Register, CIDR1
3.3.10 Component ID2 Register, CIDR2
3.3.11 Component ID3 Register, CIDR3
3.4 ATB funnel registers
3.4.1 ATB funnel register summary
3.4.2 Funnel Control register, Ctrl_Reg
3.4.3 Priority Control Register, Priority_Ctrl_Reg
3.4.4 Integration Test ATB Data0 register, ITATBDATA0
3.4.5 Integration Test ATB Control 2 Register
3.4.6 Integration Test ATB Control 1 Register, ITATBCTR1
3.4.7 Integration Test ATB Control 0 Register, ITATBCTR0
3.4.8 Integration Mode Control register, ITCTRL
3.4.9 Claim Tag Set register, CLAIMSET
3.4.10 Claim Tag Clear register, CLAIMCLR
3.4.11 Lock Access Register, LAR
3.4.12 Lock Status Register, LSR
3.4.13 Authentication Status register, AUTHSTATUS
3.4.14 Device Configuration register, DEVID
3.4.15 Device Type Identifier register, DEVTYPE
3.4.16 Peripheral ID0 Register, PIDR0
3.4.17 Peripheral ID1 Register, PIDR1
3.4.18 Peripheral ID2 Register, PIDR2
3.4.19 Peripheral ID3 Register, PIDR3
3.4.20 Peripheral ID4 Register, PIDR4
3.4.21 Component ID0 Register, CIDR0
3.4.22 Component ID1 Register, CIDR1
3.4.23 Component ID2 Register, CIDR2
3.4.24 Component ID3 Register, CIDR3
3.5 ATB replicator registers
3.5.1 ATB replicator register summary
3.5.2 ID filtering for ATB master port 0, IDFILTER0
3.5.3 ID filtering for ATB master port 1, IDFILTER1
3.5.4 Integration Mode ATB Control 0 Register, ITATBCTR0
3.5.5 Integration Mode ATB Control 1 Register, ITATBCTR1
3.5.6 Integration Mode Control register, ITCTRL
3.5.7 Claim Tag Set register, CLAIMSET
3.5.8 Claim Tag Clear register, CLAIMCLR
3.5.9 Lock Access Register, LAR
3.5.10 Lock Status Register, LSR
3.5.11 Authentication Status register, AUTHSTATUS
3.5.12 Device Configuration register, DEVID
3.5.13 Device Type Identifier register, DEVTYPE
3.5.14 Peripheral ID4 Register, PIDR4
3.5.15 Peripheral ID0 Register, PIDR0
3.5.16 Peripheral ID1 Register, PIDR1
3.5.17 Peripheral ID2 Register, PIDR2
3.5.18 Peripheral ID3 Register, PIDR3
3.5.19 Component ID0 Register, CIDR0
3.5.20 Component ID1 Register, CIDR1
3.5.21 Component ID2 Register, CIDR2
3.5.22 Component ID3 Register, CIDR3
3.6 ETB registers
3.6.1 ETB register summary
3.6.2 ETB RAM Depth register, RDP
3.6.3 ETB Status register, STS
3.6.4 ETB RAM Read Data register, RRD
3.6.5 ETB RAM Read Pointer register, RRP
3.6.6 ETB RAM Write Pointer register, RWP
3.6.7 ETB Trigger Counter register, TRG
3.6.8 ETB Control register, CTL
3.6.9 ETB RAM Write Data register, RWD
3.6.10 ETB Formatter and Flush Status Register, FFSR
3.6.11 ETB Formatter and Flush Control Register, FFCR
3.6.12 Integration Test Miscellaneous Output register 0, ITMISCOP0
3.6.13 Integration Test Trigger In and Flush In Acknowledge register, ITTRFLINACK
3.6.14 Integration Test Trigger In and Flush In register, ITTRFLIN
3.6.15 Integration Test ATB Data register 0, ITATBDATA0
3.6.16 Integration Test ATB Control Register 2, ITATBCTR2
3.6.17 Integration Test ATB Control Register 1, ITATBCTR1
3.6.18 Integration Test ATB Control Register 0, ITATBCTR0
3.6.19 Integration Mode Control register, ITCTRL
3.6.20 Claim Tag Set register, CLAIMSET
3.6.21 Claim Tag Clear register, CLAIMCLR
3.6.22 Lock Access Register, LAR
3.6.23 Lock Status Register, LSR
3.6.24 Authentication Status register, AUTHSTATUS
3.6.25 Device Configuration register, DEVID
3.6.26 Device Type Identifier register, DEVTYPE
3.6.27 Peripheral ID4 Register, PIDR4
3.6.28 Peripheral ID0 Register, PIDR0
3.6.29 Peripheral ID1 Register, PIDR1
3.6.30 Peripheral ID2 Register, PIDR2
3.6.31 Peripheral ID3 Register, PIDR3
3.6.32 Component ID0 Register, CIDR0
3.6.33 Component ID1 Register, CIDR1
3.6.34 Component ID2 Register, CIDR2
3.6.35 Component ID3 Register, CIDR3
3.7 TPIU registers
3.7.1 TPIU register summary
3.7.2 Supported Port Size register, Supported_Port_Sizes
3.7.3 Current Port Size register, Current_port_size
3.7.4 Supported Trigger Modes register, Supported_trigger_modes
3.7.5 Trigger Counter Value register, Trigger_counter_value
3.7.6 Trigger Multiplier register, Trigger_multiplier
3.7.7 Supported Test Patterns/Modes register, Supported_test_pattern_modes
3.7.8 Current Test Pattern/Modes register, Current_test_pattern_mode
3.7.9 TPIU Test Pattern Repeat Counter Register, TPRCR
3.7.10 Formatter and Flush Status Register, FFSR
3.7.11 Formatter and Flush Control Register, FFCR
3.7.12 Formatter Synchronization Counter Register, FSCR
3.7.13 TPIU EXCTL In Port register, EXTCTL_In_Port
3.7.14 TPIU EXCTL Out Port register, EXTCTL_Out_Port
3.7.15 Integration Test Trigger In and Flush In Acknowledge register, ITTRFLINACK
3.7.16 Integration Test Trigger In and Flush In register, ITTRFLIN
3.7.17 Integration Test ATB Data register 0, ITATBDATA0
3.7.18 Integration Test ATB Control Register 2, ITATBCTR2
3.7.19 Integration Test ATB Control Register 1, ITATBCTR1
3.7.20 Integration Test ATB Control Register 0, ITATBCTR0
3.7.21 Integration Mode Control register, ITCTRL
3.7.22 Claim Tag Set register, CLAIMSET
3.7.23 Claim Tag Clear register, CLAIMCLR
3.7.24 Lock Access Register, LAR
3.7.25 Lock Status Register, LSR
3.7.26 Authentication Status register, AUTHSTATUS
3.7.27 Device Configuration register, DEVID
3.7.28 Device Type Identifier register, DEVTYPE
3.7.29 Peripheral ID4 Register, PIDR4
3.7.30 Peripheral ID0 Register, PIDR0
3.7.31 Peripheral ID1 Register, PIDR1
3.7.32 Peripheral ID2 Register, PIDR2
3.7.33 Peripheral ID3 Register, PIDR3
3.7.34 Component ID0 Register, CIDR0
3.7.35 Component ID1 Register, CIDR1
3.7.36 Component ID2 Register, CIDR2
3.7.37 Component ID3 Register, CIDR3
3.8 CTI registers
3.8.1 CTI register summary table
3.8.2 CTI Control register, CTICONTROL
3.8.3 CTI Interrupt Acknowledge register, CTIINTACK
3.8.4 CTI Application Trigger Set register, CTIAPPSET
3.8.5 CTI Application Trigger Clear register, CTIAPPCLEAR
3.8.6 CTI Application Pulse register, CTIAPPPULSE
3.8.7 CTI Trigger 0 to Channel Enable register, CTIINEN0
3.8.8 CTI Trigger 1 to Channel Enable register, CTIINEN1
3.8.9 CTI Trigger 2 to Channel Enable register, CTIINEN2
3.8.10 CTI Trigger 3 to Channel Enable register, CTIINEN3
3.8.11 CTI Trigger 4 to Channel Enable register, CTIINEN4
3.8.12 CTI Trigger 5 to Channel Enable register, CTIINEN5
3.8.13 CTI Trigger 6 to Channel Enable register, CTIINEN6
3.8.14 CTI Trigger 7 to Channel Enable register, CTIINEN7
3.8.15 CTI Channel to Trigger 0 Enable register, CTIOUTEN0
3.8.16 CTI Channel to Trigger 1 Enable register, CTIOUTEN1
3.8.17 CTI Channel to Trigger 2 Enable register, CTIOUTEN2
3.8.18 CTI Channel to Trigger 3 Enable register, CTIOUTEN3
3.8.19 CTI Channel to Trigger 4 Enable register, CTIOUTEN4
3.8.20 CTI Channel to Trigger 5 Enable register, CTIOUTEN5
3.8.21 CTI Channel to Trigger 6 Enable register, CTIOUTEN6
3.8.22 CTI Channel to Trigger 7 Enable register, CTIOUTEN7
3.8.23 CTI Trigger In Status register, CTITRIGINSTATUS
3.8.24 CTI Trigger Out Status register, CTITRIGOUTSTATUS
3.8.25 CTI Channel In Status register, CTICHINSTATUS
3.8.26 CTI Channel Out Status register, CTICHOUTSTATUS
3.8.27 Enable CTI Channel Gate register, CTIGATE
3.8.28 External Multiplexer Control register, ASICCTL
3.8.29 Integration Test Channel Input Acknowledge register, ITCHINACK
3.8.30 Integration Test Trigger Input Acknowledge register, ITTRIGINACK
3.8.31 Integration Test Channel Output register, ITCHOUT
3.8.32 Integration Test Trigger Output register, ITTRIGOUT
3.8.33 Integration Test Channel Output Acknowledge register, ITCHOUTACK
3.8.34 Integration Test Trigger Output Acknowledge register, ITTRIGOUTACK
3.8.35 Integration Test Channel Input register, ITCHIN
3.8.36 Integration Test Trigger Input register, ITTRIGIN
3.8.37 Integration Mode Control register, ITCTRL
3.8.38 Claim Tag Set register, CLAIMSET
3.8.39 Claim Tag Clear register, CLAIMCLR
3.8.40 Lock Access Register, LAR
3.8.41 Lock Status Register, LSR
3.8.42 Authentication Status register, AUTHSTATUS
3.8.43 Device Configuration register, DEVID
3.8.44 Device Type Identifier register, DEVTYPE
3.8.45 Peripheral ID4 Register, PIDR4
3.8.46 Peripheral ID0 Register, PIDR0
3.8.47 Peripheral ID1 Register, PIDR1
3.8.48 Peripheral ID2 Register, PIDR2
3.8.49 Peripheral ID3 Register, PIDR3
3.8.50 Component ID0 Register, CIDR0
3.8.51 Component ID1 Register, CIDR1
3.8.52 Component ID2 Register, CIDR2
3.8.53 Component ID3 Register, CIDR3
3.9 DAP registers
3.9.1 JTAG-AP registers
3.9.2 AHB-AP registers
3.9.3 AXI-AP registers
3.9.4 APB-AP registers
3.9.5 Debug port registers
3.9.6 JTAG-DP registers
3.10 Timestamp generator
3.10.1 Timestamp generator register summary table
3.10.2 Counter Control Register, CNTCR
3.10.3 Counter Status Register, CNTSR
3.10.4 Current Counter Value Lower register, CNTCVL
3.10.5 Current Counter Value Upper register, CNTCVU
3.10.6 Base Frequency ID register, CNTFID0
3.10.7 Peripheral ID4 Register, PIDR4
3.10.8 Peripheral ID0 Register, PIDR0
3.10.9 Peripheral ID1 Register, PIDR1
3.10.10 Peripheral ID2 Register, PIDR2
3.10.11 Peripheral ID3 Register, PIDR3
3.10.12 Component ID0 Register, CIDR0
3.10.13 Component ID1 Register, CIDR1
3.10.14 Component ID2 Register, CIDR2
3.10.15 Component ID3 Register, CIDR3
4 Debug Access Port
4.1 About the Debug Access Port
4.1.1 DAP components
4.1.2 DAP flow of control
4.2 SWJ-DP
4.2.1 Auto-detect mechanism
4.2.2 Structure of the SWJ-DP
4.2.3 Operation of the SWJ-DP
4.2.4 JTAG and SWD interface
4.2.5 Operation in JTAG-DP mode
4.2.6 Operation in SW-DP mode
4.2.7 Clock, reset, and power domain support
4.2.8 SWD and JTAG selection mechanism
4.2.9 Common debug port features and registers
4.3 DAPBUS interconnect
4.3.1 Clock and reset
4.3.2 Functional interfaces
4.3.3 Operation
4.4 DAPBUS asynchronous bridge
4.4.1 Clock and reset
4.4.2 Functional interfaces
4.4.3 Functional description
4.4.4 Low-power features
4.5 DAPBUS synchronous bridge
4.5.1 Clock and reset
4.5.2 Functional interface
4.5.3 Functional description
4.5.4 Low power features
4.6 JTAG-AP
4.6.1 External interfaces
4.6.2 RTCK connections
4.7 AXI-AP
4.7.1 Clock and reset
4.7.2 Functional interfaces
4.7.3 AXI-AP features
4.7.4 DAP transfer abort
4.7.5 Error responses
4.7.6 AXI transfers
4.7.7 Packed transfers
4.7.8 Valid combinations of AxCACHE and AxDOMAIN table
4.8 AHB-AP
4.8.1 Clock and reset
4.8.2 External interfaces
4.8.3 Interfacing an AHB5 slave to the cxdapahbap
4.8.4 Implementation features
4.8.5 DAP transfers
4.8.6 Differentiation between system and access port initiated error responses
4.9 APB-AP
4.9.1 Clock and reset
4.9.2 External interfaces
4.9.3 Implementation features
4.9.4 DAP transfers
4.9.5 Authentication requirements for APB-AP
5 APB Interconnect Components
5.1 APB Interconnect with ROM table
5.1.1 Clock and reset
5.1.2 Functional interfaces
5.1.3 Device operation
5.2 APB asynchronous bridge
5.2.1 Clock and reset
5.2.2 Functional interfaces
5.2.3 Low-power features
5.3 APB synchronous bridge
5.3.1 Clock and reset
5.3.2 Functional interface
5.3.3 Functional description
5.3.4 Low-power features
6 ATB Interconnect Components
6.1 ATB replicator
6.1.1 Clock and reset
6.1.2 Functional interfaces
6.1.3 Functional overview
6.2 ATB funnel
6.2.1 Clock and reset
6.2.2 Functional interface
6.2.3 ATB slave interface enable
6.2.4 Arbitration
6.2.5 Cascaded funnel support
6.2.6 Topology detection
6.2.7 Non-programmable funnel
6.3 ATB upsizer
6.3.1 Clocks and reset
6.3.2 Functional interface
6.3.3 Component functionality
6.4 ATB downsizer
6.4.1 Clocks and reset
6.4.2 Functional interface
6.4.3 Component functionality
6.5 ATB asynchronous bridge
6.5.1 Functional interfaces
6.5.2 Clocks and resets
6.5.3 Device operation
6.5.4 Low-power features
6.6 ATB synchronous bridge
6.6.1 Clock and reset
6.6.2 Functional interfaces
6.6.3 Operation
6.6.4 Low-power control
7 Timestamp Components
7.1 About the timestamp components
7.2 Timestamp generator
7.2.1 Clock and reset
7.2.2 Processor generic time
7.2.3 Control APB interface
7.2.4 Read-only APB interface
7.2.5 hltdbg signal
7.2.6 Counter overflow
7.3 Timestamp encoder
7.3.1 Clock and reset
7.4 Narrow timestamp replicator
7.4.1 Clock and reset
7.5 Narrow timestamp asynchronous bridge
7.5.1 Functional interfaces
7.5.2 Clocks and resets
7.5.3 Operation
7.5.4 Low-power features
7.5.5 Timestamp recovery from stopped clock
7.6 Narrow timestamp synchronous bridge
7.6.1 Functional interfaces
7.6.2 Clocks and resets
7.6.3 Functionality
7.6.4 Low-power features
7.7 Timestamp decoder
7.7.1 Clock and reset
7.8 Timestamp interpolator
7.8.1 Clock and reset
7.8.2 Functional interface
7.8.3 Limitations
8 Embedded Cross Trigger
8.1 Cross-triggering components
8.1.1 Event signaling protocol
8.2 CTI
8.2.1 Clocks and resets
8.2.2 Functional interface
8.2.3 Disabling a CTI
8.2.4 Authentication
8.3 CTM
8.3.1 Clocks and resets
8.3.2 Functional interface
8.4 Event asynchronous bridge
8.4.1 Clocks and resets
8.4.2 Connecting eventack signals
8.5 Register slice
8.6 Channel asynchronous bridge
8.7 Cross Trigger to System Trace Macrocell
9 Trace Port Interface Unit
9.1 About the Trace Port Interface Unit
9.2 Clocks and resets
9.3 Functional interfaces
9.4 Trace out port
9.4.1 Signals of the trace out port
9.4.2 traceclk alignment
9.4.3 tracectl removal
9.4.4 tracectl encoding
9.4.5 Off-chip based traceclkin
9.5 Trace port triggers
9.5.1 Correlation with afvalid
9.6 Programming the TPIU for trace capture
9.7 Example configuration scenarios
9.7.1 Capturing trace after an event and stopping
9.7.2 Only indicating triggers and continuing to flush
9.7.3 Multiple trigger indications
9.7.4 Independent triggering and flushing
9.8 TPIU pattern generator
9.8.1 Pattern generator modes of operation
9.8.2 Supported options
10 Embedded Trace Buffer
10.1 About the ETB
10.2 Clocks and resets
10.3 Functional Interfaces
10.3.1 Cross-triggering events
10.3.2 Memory BIST interface
10.4 ETB trace capture and formatting
10.4.1 Modes of operation
10.4.2 Stopping trace
10.4.3 Flush assertion
10.4.4 Triggers
10.5 ETB RAM support
10.5.1 Access sizes
10.5.2 BIST interface
10.5.3 RAM instantiation
11 Granular Power Requester
11.1 Granular Power Requester interfaces
11.1.1 Clock and reset
11.1.2 Functional interfaces
11.1.3 Device unlocking
A Signal Descriptions
A.1 Debug Access Port signals
A.1.1 Serial wire or JTAG Debug Port signals
A.1.2 DAPBUS interconnect signals
A.1.3 DAPBUS asynchronous bridge signals
A.1.4 DAPBUS synchronous bridge signals
A.1.5 JTAG - Access Port signals
A.1.6 AXI - Access Port signals
A.1.7 AHB - Access Port signals
A.1.8 APB - Access Port signals
A.2 APB component signals
A.2.1 APB interconnect signals
A.2.2 APB asynchronous bridge signals
A.2.3 APB synchronous bridge signals
A.3 ATB interconnect signals
A.3.1 ATB replicator signals
A.3.2 ATB trace funnel signals
A.3.3 ATB upsizer signals
A.3.4 ATB downsizer signals
A.3.5 ATB asynchronous bridge signals
A.3.6 ATB synchronous bridge signals
A.4 Timestamp component signals
A.4.1 Timestamp generator signals
A.4.2 Timestamp encoder signals
A.4.3 Narrow timestamp replicator signals
A.4.4 Narrow timestamp asynchronous bridge signals
A.4.5 Narrow timestamp synchronous bridge signals
A.4.6 Timestamp decoder signals
A.4.7 Timestamp interpolator signals
A.5 Trigger component signals
A.5.1 Cross Trigger Interface signals
A.5.2 Cross Trigger Matrix signals
A.5.3 Event asynchronous bridge signals
A.6 Trace sink signals
A.6.1 Trace Port Interface Unit signals
A.6.2 Embedded Trace Buffer signals
A.7 Authentication and event bridges
A.7.1 Authentication asynchronous bridge signals
A.7.2 Authentication synchronous bridge signals
A.7.3 Authentication replicator
A.8 Granular power requester signals
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
A 04 November 2011 Non-Confidential First release for r0p0
B 16 April 2012 Non-Confidential First release for r1p0
C 27 September 2012 Non-Confidential First release for r2p0
D 14 December 2012 Non-Confidential First release for r2p1
E 28 June 2013 Non-Confidential First release for r3p0
F 26 September 2013 Non-Confidential First release for r3p1
G 16 March 2015 Non-Confidential First release for r3p2 (product revision r3p2-00rel0)
0302-01 17 June 2016 Non-Confidential Second release for r3p2 (product revision r3p2-00rel1)

Non-Confidential Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.
Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.
THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.
This document may include technical inaccuracies or typographical errors.
TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice.
If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.
Copyright © 2011-2013, 2015, 2016, ARM Limited or its affiliates. All rights reserved.
ARM Limited. Company 02557590 registered in England.
110 Fulbourn Road, Cambridge, England CB1 9NJ.
LES-PRE-20349

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.
Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is Final, that is for a developed product.

Web Address

Non-ConfidentialPDF file icon PDF versionARM 100536_0302_01_en
Copyright © 2011-2013, 2015, 2016 ARM. All rights reserved.