2.3.5 Low-power clock control interface

This section describes the clock requirements for the DMC-620.

The DMC-620 provides a low-power control interface using the Q-Channel protocol. The low-power control interface is used to place the DMC into its low-power state, where the clock can be removed. The system can use the APB interface to put the DMC into its low-power state, and take it out of its low-power state.

Q-Channel interface

The DMC has a Q-Channel interface that allows an external power controller to place the DMC into a low-power state.

It is a standard Q-Channel interface as defined in the ARM® Low Power Interface Specification, Q-Channel and P-Channel Interfaces using the following signals:

  • qactive.
  • qreqn.
  • qacceptn.
  • qdeny.

When the DMC receives a request, it puts the DRAM into self_refresh before asserting qacceptn to accept the request that indicates the clk can be stopped.

The DMC denies requests to power down using the Q-Channel when geardown_mode is enabled. In this case, low-power mode can still be entered using the APB interface.

There is a separate Q-Channel interface for the pclk using the following signals:

  • qactive_apb.
  • qreqn_apb.
  • qacceptn_apb.
  • qdeny_apb.

The DMC never denies a request to power down the APB clock although it might be delayed based on APB activity.

Note:

These two interfaces are interrelated and a change on one can cause qactive on the other to be asserted. If this occurs, then the powerup request must be responded to in a timely fashion to allow the request to be serviced.

See ARM® Low Power Interface Specification, Q-Channel and P-Channel Interfaces.

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