The DMC-620 supports DDR3 and DDR4 SDRAMs. It also supports error checking, reliability, availability, and serviceability features. In addition, Quality of Service (QoS) features and ARM® TrustZone® architecture security extensions are built in throughout the controller.
The DMC-620 has the
- Profiling signals that enable performance profiling to be performed
in the system.
- TrustZone architecture security extensions.
- Buffering to optimize read and write turnaround, and to maximize
- A System Interface (SI) that provides:
- A CHI interface to connect to a CoreLink™
Cache Coherent Network (CCN) or a CoreLink
Coherent Mesh Network (CMN).
- An AMBA®5 CHI
interface supporting the CHI-A and CHI-B architecture.
- An APB interface for configuration and initialization.
- An external performance event interface for connecting to
CoreSight™ on-chip debug and trace technology.
- A 128-bit or 256-bit CHI interface.
- A Memory Interface (MI) that provides:
- A DFI 3.1 and 4.0 interface to a PHY that supports DDR3,
DDR3L, and DDR4.
- Support for 1:2 DFI frequency ratio mode.
- Support for either a 32-bit wide data SDRAM interface or a
64-bit wide data SDRAM interface.
- Low-power operation through programmable SDRAM power modes.
- ARMv8.2 compatible Reliability, Availability,
- Single Error Correcting, Double Error
Detecting (SECDED) Error-Correcting Code (ECC) for off-chip
- Symbol-based ECC, to correct memory chip and data-lane
- SECDED ECC for on-chip RAM protection.
- Supports ARMv8.2 end-to-end RAS protection, data poisoning, and
- Hardware Read-Modify-Write
(RMW) for systems supporting sparse writes.
- Command-Address (CA) parity checks for DDR3
and DDR4 link faults.
- CRC write-data protection for DDR4 devices.
- A programmable mechanism for automated SDRAM scrubbing.
- Error handling and automated recovery.
- Power Control Logic (PCL) that generates powerdown requests to the SDRAM, and
manages power enables for the PHY logic.
- 3DS support for 8H, 4H, and 2H devices.
- DDR4 Registered Dual In-line Memory Module (RDIMM) and
Load-Reduced Dual In-line Memory Module (LRDIMM) support.
- Flexible Dual In-line Memory Module (DIMM) topology support:
- Signal multiplexing that allows a single board layout to support different
RDIMM device types (3DS or planer), and a different number of devices.
- Support for RDIMM Encoded or Direct CS.
- Core to DMC Prefetch Hint direct path allowing the core to
directly initiate a DMC prefetch.
- Configurable out-of-order request queue depth and symbol ECC logic.