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Determines the Mode Register command that the DMC must use to put the DRAM into a training mode for write leveling. You enable this function with the wrlvl_control Register. See the PHY training interface section of the Integration Manual for more information. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The wrlvl_mrs_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.