|Non-Confidential||PDF version||ARM 100568_0000_01_en|
|Home > Programmers Model > Register descriptions > err4misc1|
This register gives the bank and logical rank, and DBID of the last error detected before an interrupt is asserted. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The err4misc1 register characteristics are:
There are no usage constraints.
There is only one DMC configuration.