The DMC-620 has the following external interfaces:

• A system interface to provide read and write access to or from a master that supports either the CHI-A or CHI-B protocol.
• An APB3 programmers interface to program and control the DMC-620.
• A DFI-compatible PHY interface to transfer data to and from the external memory.
• A profile and debug interface.
• A low-power clock control interface that uses the Q-Channel protocol. See Q-Channel interface.
• An abort interface that is a four-phase request and acknowledge handshake. The abort interface can be used to recover from a livelock when DRAM or PHY fails.
• User I/O ports.
• A set of interrupts that are used to report operational events and detected faults.