2.2 Clocking and resets

The DMC-620 normally operates as one synchronous clock domain between the interconnect and the external DDR interface. However, the programming interface can operate asynchronously to this.

This section shows the clock and reset signals that the DMC-620 requires.


There are either two or three clock inputs depending on the DFI frequency ratio configuration:

  • clk. This is the main DMC clock that runs at SDRAM clock frequency. It must run synchronous to, and at the same frequency, as the CHI interface. If the CHI interface is not running at SDRAM clock frequency, then a Device Source Synchronous Bridge (DSSB), which is part of the CCN product must be used. When in a 1:1 DFI frequency ratio mode, this clock also serves as the dfi clk.

  • dfi_clk. This clock port only exists if the DMC is in 1:2 or 1:4 mode. The clock runs the DFI interface and connects to both the DMC and the PHY. It must be edge synchronous to clk, and run at half the clk frequency if it is in the 1:2 configuration or one quarter the clk frequency when in the 1:4 configuration.

  • pclk. This can run asynchronously to clk and dfi clk.


Resets must be applied for a minimum duration of 16 clock cycles for each clock domain.

There are two reset inputs. RESETn resets both clk and dfi clk registers and PRESETn resets pclk registers. The pclk domain must be brought out of reset prior to the clk and dfi clk domains.


  • To assert any DMC-620 reset signal, you must set it LOW.
  • To perform a DMC-620 reset, you must assert both reset signals.
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