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This book is for the ARM® CoreLink™ DMC-620 Dynamic Memory Controller.
n identifier indicates the revision status of the product described in this book, for example, r
|r||Identifies the major revision of the product, for example, r1.|
|p||Identifies the minor revision or modification status of the product, for example, p2.|
This book is written for experienced hardware engineers who want to integrate the delivered ARM System on Chip (SoC) product in a SoC design.
This book is organized into the following chapters:
This chapter describes the DMC-620.
This chapter describes how the DMC-620 operates.
This chapter describes the programmers model of the DMC-620.
This appendix describes the DMC-620 signals.
This appendix describes the technical changes between released issues of this book.
The ARM Glossary is a list of terms used in ARM documentation, together with definitions for those terms. The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning.
See the ARM Glossary for more information.
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.
Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.
The signal conventions are:
The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:
HIGH for active-HIGH signals.
LOW for active-LOW signals.
At the start or end of a signal name denotes an active-LOW signal.
This book contains information that is specific to this product. See the following documents for other relevant information.
The following confidential books are only available to licensees: