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Determines the Mode Register command to use to place the DRAM into a VrefDQ training mode as part of WrDQ training, when enabled by the wdqlvl_control register. You enable this function with the wdqlvl_control Register. See the PHY training interface section of the Integration Manual for more information. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The wdqlvl_vrefdq_train_mrs_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.