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Configures the write-to-read timing parameter, for both same chip, other bank group (tWTR_s), same chip, same bank group (t_WTR_l), and alternate chip (tWTR_cs). Note: these must take into account CRC timing requirements. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
The t_wtr_now register characteristics are:
There are no usage constraints.
There is only one DMC configuration.