ARM® CoreLink™ DMC-620 Dynamic Memory Controller Technical Reference Manual

Revision r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the product
1.2 DMC-620 compliance
1.3 Features
1.4 Interfaces
1.5 Configurable options
1.6 Test features
1.7 Product documentation and design flow
1.8 Product revisions
2 Functional Description
2.1 About the functions
2.2 Clocking and resets
2.3 Interfaces
2.3.1 System interface
2.3.2 Programming interface
2.3.3 PHY interface
2.3.4 Profile and debug interface
2.3.5 Low-power clock control interface
2.3.6 Abort interface
2.4 Constraints and limitations of use
3 Programmers Model
3.1 About this programmers model
3.2 Register summary
3.3 Register descriptions
3.3.1 memc_status
3.3.2 memc_config
3.3.3 memc_cmd
3.3.4 address_control_next
3.3.5 decode_control_next
3.3.6 format_control
3.3.7 address_map_next
3.3.8 low_power_control_next
3.3.9 turnaround_control_next
3.3.10 hit_turnaround_control_next
3.3.11 qos_class_control_next
3.3.12 escalation_control_next
3.3.13 qv_control_31_00_next
3.3.14 qv_control_63_32_next
3.3.15 rt_control_31_00_next
3.3.16 rt_control_63_32_next
3.3.17 timeout_control_next
3.3.18 credit_control_next
3.3.19 write_priority_control_31_00_next
3.3.20 write_priority_control_63_32_next
3.3.21 queue_threshold_control_31_00_next
3.3.22 queue_threshold_control_63_32_next
3.3.23 address_shutter_31_00_next
3.3.24 address_shutter_63_32_next
3.3.25 address_shutter_95_64_next
3.3.26 address_shutter_127_96_next
3.3.27 address_shutter_159_128_next
3.3.28 address_shutter_191_160_next
3.3.29 memory_address_max_31_00_next
3.3.30 memory_address_max_47_32_next
3.3.31 access_address_min0_31_00_next
3.3.32 access_address_min0_47_32_next
3.3.33 access_address_max0_31_00_next
3.3.34 access_address_max0_47_32_next
3.3.35 access_address_min1_31_00_next
3.3.36 access_address_min1_47_32_next
3.3.37 access_address_max1_31_00_next
3.3.38 access_address_max1_47_32_next
3.3.39 access_address_min2_31_00_next
3.3.40 access_address_min2_47_32_next
3.3.41 access_address_max2_31_00_next
3.3.42 access_address_max2_47_32_next
3.3.43 access_address_min3_31_00_next
3.3.44 access_address_min3_47_32_next
3.3.45 access_address_max3_31_00_next
3.3.46 access_address_max3_47_32_next
3.3.47 access_address_min4_31_00_next
3.3.48 access_address_min4_47_32_next
3.3.49 access_address_max4_31_00_next
3.3.50 access_address_max4_47_32_next
3.3.51 access_address_min5_31_00_next
3.3.52 access_address_min5_47_32_next
3.3.53 access_address_max5_31_00_next
3.3.54 access_address_max5_47_32_next
3.3.55 access_address_min6_31_00_next
3.3.56 access_address_min6_47_32_next
3.3.57 access_address_max6_31_00_next
3.3.58 access_address_max6_47_32_next
3.3.59 access_address_min7_31_00_next
3.3.60 access_address_min7_47_32_next
3.3.61 access_address_max7_31_00_next
3.3.62 access_address_max7_47_32_next
3.3.63 channel_status
3.3.64 channel_status_63_32
3.3.65 direct_addr
3.3.66 direct_cmd
3.3.67 dci_replay_type_next
3.3.68 direct_control_next
3.3.69 dci_strb
3.3.70 dci_data
3.3.71 refresh_control_next
3.3.72 memory_type_next
3.3.73 feature_config
3.3.74 nibble_failed_031_000
3.3.75 nibble_failed_063_032
3.3.76 nibble_failed_095_064
3.3.77 nibble_failed_127_096
3.3.78 queue_allocate_control_031_000
3.3.79 queue_allocate_control_063_032
3.3.80 queue_allocate_control_095_064
3.3.81 queue_allocate_control_127_096
3.3.82 link_err_count
3.3.83 scrub_control0_next
3.3.84 scrub_address_min0_next
3.3.85 scrub_address_max0_next
3.3.86 scrub_address_current0
3.3.87 scrub_control1_next
3.3.88 scrub_address_min1_next
3.3.89 scrub_address_max1_next
3.3.90 scrub_address_current1
3.3.91 cs_remap_control_31_00_next
3.3.92 cs_remap_control_63_32_next
3.3.93 cs_remap_control_95_64_next
3.3.94 cs_remap_control_127_96_next
3.3.95 cid_remap_control_31_00_next
3.3.96 cid_remap_control_63_32_next
3.3.97 cke_remap_control_next
3.3.98 rst_remap_control_next
3.3.99 ck_remap_control_next
3.3.100 power_group_control_31_00_next
3.3.101 power_group_control_63_32_next
3.3.102 power_group_control_95_64_next
3.3.103 power_group_control_127_96_next
3.3.104 phy_rdwrdata_cs_mask_31_00
3.3.105 phy_rdwrdata_cs_mask_63_32
3.3.106 phy_request_cs_remap
3.3.107 feature_control_next
3.3.108 mux_control_next
3.3.109 rank_remap_control_next
3.3.110 t_refi_next
3.3.111 t_rfc_next
3.3.112 t_mrr_next
3.3.113 t_mrw_next
3.3.114 t_rcd_next
3.3.115 t_ras_next
3.3.116 t_rp_next
3.3.117 t_rpall_next
3.3.118 t_rrd_next
3.3.119 t_act_window_next
3.3.120 t_rtr_next
3.3.121 t_rtw_next
3.3.122 t_rtp_next
3.3.123 t_wr_next
3.3.124 t_wtr_next
3.3.125 t_wtw_next
3.3.126 t_xmpd_next
3.3.127 t_ep_next
3.3.128 t_xp_next
3.3.129 t_esr_next
3.3.130 t_xsr_next
3.3.131 t_esrck_next
3.3.132 t_ckxsr_next
3.3.133 t_cmd_next
3.3.134 t_parity_next
3.3.135 t_zqcs_next
3.3.136 t_rw_odt_clr_next
3.3.137 t_rddata_en_next
3.3.138 t_phyrdlat_next
3.3.139 t_phywrlat_next
3.3.140 rdlvl_control_next
3.3.141 rdlvl_mrs_next
3.3.142 t_rdlvl_en_next
3.3.143 t_rdlvl_rr_next
3.3.144 wrlvl_control_next
3.3.145 wrlvl_mrs_next
3.3.146 t_wrlvl_en_next
3.3.147 t_wrlvl_ww_next
3.3.148 training_wrlvl_slice_status
3.3.149 training_rdlvl_slice_status
3.3.150 training_rdlvl_gate_slice_status
3.3.151 training_wdqlvl_slice_status
3.3.152 training_wdqlvl_slice_result
3.3.153 phy_power_control_next
3.3.154 t_lpresp_next
3.3.155 phy_update_control_next
3.3.156 t_odth_next
3.3.157 odt_timing_next
3.3.158 odt_wr_control_31_00_next
3.3.159 odt_wr_control_63_32_next
3.3.160 odt_rd_control_31_00_next
3.3.161 odt_rd_control_63_32_next
3.3.162 temperature_readout
3.3.163 training_status
3.3.164 training_status_63_32
3.3.165 dq_map_control_15_00_next
3.3.166 dq_map_control_31_16_next
3.3.167 dq_map_control_47_32_next
3.3.168 dq_map_control_63_48_next
3.3.169 dq_map_control_71_64_next
3.3.170 rank_status
3.3.171 mode_change_status
3.3.172 odt_cp_control_31_00_next
3.3.173 odt_cp_control_63_32_next
3.3.174 user_status
3.3.175 user_config0_next
3.3.176 user_config1_next
3.3.177 user_config2
3.3.178 user_config3
3.3.179 interrupt_control
3.3.180 interrupt_clr
3.3.181 interrupt_status
3.3.182 failed_access_int_info_31_00
3.3.183 failed_access_int_info_63_32
3.3.184 failed_prog_int_info_31_00
3.3.185 failed_prog_int_info_63_32
3.3.186 link_err_int_info_31_00
3.3.187 link_err_int_info_63_32
3.3.188 arch_fsm_int_info_31_00
3.3.189 arch_fsm_int_info_63_32
3.3.190 t_db_train_resp_next
3.3.191 t_lvl_disconnect_next
3.3.192 wdqlvl_control_next
3.3.193 wdqlvl_vrefdq_train_mrs_next
3.3.194 wdqlvl_address_31_00_next
3.3.195 wdqlvl_address_63_32_next
3.3.196 t_wdqlvl_en_next
3.3.197 t_wdqlvl_ww_next
3.3.198 t_wdqlvl_rw_next
3.3.199 training_wdqlvl_slice_resp
3.3.200 training_rdlvl_slice_resp
3.3.201 phymstr_control_next
3.3.202 err0fr
3.3.203 err0ctlr0
3.3.204 err0ctlr1
3.3.205 err0status
3.3.206 err1fr
3.3.207 err1ctlr
3.3.208 err1status
3.3.209 err1addr0
3.3.210 err1addr1
3.3.211 err1misc0
3.3.212 err1misc1
3.3.213 err1misc2
3.3.214 err1misc3
3.3.215 err1misc4
3.3.216 err1misc5
3.3.217 err2fr
3.3.218 err2ctlr
3.3.219 err2status
3.3.220 err2addr0
3.3.221 err2addr1
3.3.222 err2misc0
3.3.223 err2misc1
3.3.224 err2misc2
3.3.225 err2misc3
3.3.226 err2misc4
3.3.227 err2misc5
3.3.228 err3fr
3.3.229 err3ctlr
3.3.230 err3status
3.3.231 err3addr0
3.3.232 err3addr1
3.3.233 err4fr
3.3.234 err4ctlr
3.3.235 err4status
3.3.236 err4addr0
3.3.237 err4addr1
3.3.238 err4misc0
3.3.239 err4misc1
3.3.240 err4misc2
3.3.241 err5fr
3.3.242 err5ctlr
3.3.243 err5status
3.3.244 err5addr0
3.3.245 err5addr1
3.3.246 err5misc0
3.3.247 err5misc1
3.3.248 err5misc2
3.3.249 err6fr
3.3.250 err6ctlr
3.3.251 err6status
3.3.252 err6addr0
3.3.253 err6addr1
3.3.254 err6misc0
3.3.255 err6misc1
3.3.256 errgsr
3.3.257 pmu_snapshot_req
3.3.258 pmu_snapshot_ack
3.3.259 pmu_overflow_status_clkdiv2
3.3.260 pmu_overflow_status_clk
3.3.261 pmu_clkdiv2_counter_0_mask_31_00
3.3.262 pmu_clkdiv2_counter_0_mask_63_32
3.3.263 pmu_clkdiv2_counter_0_match_31_00
3.3.264 pmu_clkdiv2_counter_0_match_63_32
3.3.265 pmu_clkdiv2_counter_0_control
3.3.266 pmu_clkdiv2_counter_0_snapshot_value_31_00
3.3.267 pmu_clkdiv2_counter_0_value_31_00
3.3.268 pmu_clkdiv2_counter_1_mask_31_00
3.3.269 pmu_clkdiv2_counter_1_mask_63_32
3.3.270 pmu_clkdiv2_counter_1_match_31_00
3.3.271 pmu_clkdiv2_counter_1_match_63_32
3.3.272 pmu_clkdiv2_counter_1_control
3.3.273 pmu_clkdiv2_counter_1_snapshot_value_31_00
3.3.274 pmu_clkdiv2_counter_1_value_31_00
3.3.275 pmu_clkdiv2_counter_2_mask_31_00
3.3.276 pmu_clkdiv2_counter_2_mask_63_32
3.3.277 pmu_clkdiv2_counter_2_match_31_00
3.3.278 pmu_clkdiv2_counter_2_match_63_32
3.3.279 pmu_clkdiv2_counter_2_control
3.3.280 pmu_clkdiv2_counter_2_snapshot_value_31_00
3.3.281 pmu_clkdiv2_counter_2_value_31_00
3.3.282 pmu_clkdiv2_counter_3_mask_31_00
3.3.283 pmu_clkdiv2_counter_3_mask_63_32
3.3.284 pmu_clkdiv2_counter_3_match_31_00
3.3.285 pmu_clkdiv2_counter_3_match_63_32
3.3.286 pmu_clkdiv2_counter_3_control
3.3.287 pmu_clkdiv2_counter_3_snapshot_value_31_00
3.3.288 pmu_clkdiv2_counter_3_value_31_00
3.3.289 pmu_clkdiv2_counter_4_mask_31_00
3.3.290 pmu_clkdiv2_counter_4_mask_63_32
3.3.291 pmu_clkdiv2_counter_4_match_31_00
3.3.292 pmu_clkdiv2_counter_4_match_63_32
3.3.293 pmu_clkdiv2_counter_4_control
3.3.294 pmu_clkdiv2_counter_4_snapshot_value_31_00
3.3.295 pmu_clkdiv2_counter_4_value_31_00
3.3.296 pmu_clkdiv2_counter_5_mask_31_00
3.3.297 pmu_clkdiv2_counter_5_mask_63_32
3.3.298 pmu_clkdiv2_counter_5_match_31_00
3.3.299 pmu_clkdiv2_counter_5_match_63_32
3.3.300 pmu_clkdiv2_counter_5_control
3.3.301 pmu_clkdiv2_counter_5_snapshot_value_31_00
3.3.302 pmu_clkdiv2_counter_5_value_31_00
3.3.303 pmu_clkdiv2_counter_6_mask_31_00
3.3.304 pmu_clkdiv2_counter_6_mask_63_32
3.3.305 pmu_clkdiv2_counter_6_match_31_00
3.3.306 pmu_clkdiv2_counter_6_match_63_32
3.3.307 pmu_clkdiv2_counter_6_control
3.3.308 pmu_clkdiv2_counter_6_snapshot_value_31_00
3.3.309 pmu_clkdiv2_counter_6_value_31_00
3.3.310 pmu_clkdiv2_counter_7_mask_31_00
3.3.311 pmu_clkdiv2_counter_7_mask_63_32
3.3.312 pmu_clkdiv2_counter_7_match_31_00
3.3.313 pmu_clkdiv2_counter_7_match_63_32
3.3.314 pmu_clkdiv2_counter_7_control
3.3.315 pmu_clkdiv2_counter_7_snapshot_value_31_00
3.3.316 pmu_clkdiv2_counter_7_value_31_00
3.3.317 pmu_clk_counter_0_mask_31_00
3.3.318 pmu_clk_counter_0_mask_63_32
3.3.319 pmu_clk_counter_0_match_31_00
3.3.320 pmu_clk_counter_0_match_63_32
3.3.321 pmu_clk_counter_0_control
3.3.322 pmu_clk_counter_0_snapshot_value_31_00
3.3.323 pmu_clk_counter_0_value_31_00
3.3.324 pmu_clk_counter_1_mask_31_00
3.3.325 pmu_clk_counter_1_mask_63_32
3.3.326 pmu_clk_counter_1_match_31_00
3.3.327 pmu_clk_counter_1_match_63_32
3.3.328 pmu_clk_counter_1_control
3.3.329 pmu_clk_counter_1_snapshot_value_31_00
3.3.330 pmu_clk_counter_1_value_31_00
3.3.331 integ_cfg
3.3.332 integ_outputs
3.3.333 address_control_now
3.3.334 decode_control_now
3.3.335 address_map_now
3.3.336 low_power_control_now
3.3.337 turnaround_control_now
3.3.338 hit_turnaround_control_now
3.3.339 qos_class_control_now
3.3.340 escalation_control_now
3.3.341 qv_control_31_00_now
3.3.342 qv_control_63_32_now
3.3.343 rt_control_31_00_now
3.3.344 rt_control_63_32_now
3.3.345 timeout_control_now
3.3.346 credit_control_now
3.3.347 write_priority_control_31_00_now
3.3.348 write_priority_control_63_32_now
3.3.349 queue_threshold_control_31_00_now
3.3.350 queue_threshold_control_63_32_now
3.3.351 address_shutter_31_00_now
3.3.352 address_shutter_63_32_now
3.3.353 address_shutter_95_64_now
3.3.354 address_shutter_127_96_now
3.3.355 address_shutter_159_128_now
3.3.356 address_shutter_191_160_now
3.3.357 memory_address_max_31_00_now
3.3.358 memory_address_max_47_32_now
3.3.359 access_address_min0_31_00_now
3.3.360 access_address_min0_47_32_now
3.3.361 access_address_max0_31_00_now
3.3.362 access_address_max0_47_32_now
3.3.363 access_address_min1_31_00_now
3.3.364 access_address_min1_47_32_now
3.3.365 access_address_max1_31_00_now
3.3.366 access_address_max1_47_32_now
3.3.367 access_address_min2_31_00_now
3.3.368 access_address_min2_47_32_now
3.3.369 access_address_max2_31_00_now
3.3.370 access_address_max2_47_32_now
3.3.371 access_address_min3_31_00_now
3.3.372 access_address_min3_47_32_now
3.3.373 access_address_max3_31_00_now
3.3.374 access_address_max3_47_32_now
3.3.375 access_address_min4_31_00_now
3.3.376 access_address_min4_47_32_now
3.3.377 access_address_max4_31_00_now
3.3.378 access_address_max4_47_32_now
3.3.379 access_address_min5_31_00_now
3.3.380 access_address_min5_47_32_now
3.3.381 access_address_max5_31_00_now
3.3.382 access_address_max5_47_32_now
3.3.383 access_address_min6_31_00_now
3.3.384 access_address_min6_47_32_now
3.3.385 access_address_max6_31_00_now
3.3.386 access_address_max6_47_32_now
3.3.387 access_address_min7_31_00_now
3.3.388 access_address_min7_47_32_now
3.3.389 access_address_max7_31_00_now
3.3.390 access_address_max7_47_32_now
3.3.391 dci_replay_type_now
3.3.392 direct_control_now
3.3.393 refresh_control_now
3.3.394 memory_type_now
3.3.395 scrub_control0_now
3.3.396 scrub_address_min0_now
3.3.397 scrub_address_max0_now
3.3.398 scrub_control1_now
3.3.399 scrub_address_min1_now
3.3.400 scrub_address_max1_now
3.3.401 cs_remap_control_31_00_now
3.3.402 cs_remap_control_63_32_now
3.3.403 cs_remap_control_95_64_now
3.3.404 cs_remap_control_127_96_now
3.3.405 cid_remap_control_31_00_now
3.3.406 cid_remap_control_63_32_now
3.3.407 cke_remap_control_now
3.3.408 rst_remap_control_now
3.3.409 ck_remap_control_now
3.3.410 power_group_control_31_00_now
3.3.411 power_group_control_63_32_now
3.3.412 power_group_control_95_64_now
3.3.413 power_group_control_127_96_now
3.3.414 feature_control_now
3.3.415 mux_control_now
3.3.416 rank_remap_control_now
3.3.417 t_refi_now
3.3.418 t_rfc_now
3.3.419 t_mrr_now
3.3.420 t_mrw_now
3.3.421 t_rcd_now
3.3.422 t_ras_now
3.3.423 t_rp_now
3.3.424 t_rpall_now
3.3.425 t_rrd_now
3.3.426 t_act_window_now
3.3.427 t_rtr_now
3.3.428 t_rtw_now
3.3.429 t_rtp_now
3.3.430 t_wr_now
3.3.431 t_wtr_now
3.3.432 t_wtw_now
3.3.433 t_xmpd_now
3.3.434 t_ep_now
3.3.435 t_xp_now
3.3.436 t_esr_now
3.3.437 t_xsr_now
3.3.438 t_esrck_now
3.3.439 t_ckxsr_now
3.3.440 t_cmd_now
3.3.441 t_parity_now
3.3.442 t_zqcs_now
3.3.443 t_rw_odt_clr_now
3.3.444 t_rddata_en_now
3.3.445 t_phyrdlat_now
3.3.446 t_phywrlat_now
3.3.447 rdlvl_control_now
3.3.448 rdlvl_mrs_now
3.3.449 t_rdlvl_en_now
3.3.450 t_rdlvl_rr_now
3.3.451 wrlvl_control_now
3.3.452 wrlvl_mrs_now
3.3.453 t_wrlvl_en_now
3.3.454 t_wrlvl_ww_now
3.3.455 phy_power_control_now
3.3.456 t_lpresp_now
3.3.457 phy_update_control_now
3.3.458 t_odth_now
3.3.459 odt_timing_now
3.3.460 odt_wr_control_31_00_now
3.3.461 odt_wr_control_63_32_now
3.3.462 odt_rd_control_31_00_now
3.3.463 odt_rd_control_63_32_now
3.3.464 dq_map_control_15_00_now
3.3.465 dq_map_control_31_16_now
3.3.466 dq_map_control_47_32_now
3.3.467 dq_map_control_63_48_now
3.3.468 dq_map_control_71_64_now
3.3.469 odt_cp_control_31_00_now
3.3.470 odt_cp_control_63_32_now
3.3.471 user_config0_now
3.3.472 user_config1_now
3.3.473 t_db_train_resp_now
3.3.474 t_lvl_disconnect_now
3.3.475 wdqlvl_control_now
3.3.476 wdqlvl_vrefdq_train_mrs_now
3.3.477 wdqlvl_address_31_00_now
3.3.478 wdqlvl_address_63_32_now
3.3.479 t_wdqlvl_en_now
3.3.480 t_wdqlvl_ww_now
3.3.481 t_wdqlvl_rw_now
3.3.482 phymstr_control_now
3.3.483 periph_id_4
3.3.484 periph_id_0
3.3.485 periph_id_1
3.3.486 periph_id_2
3.3.487 periph_id_3
3.3.488 component_id_0
3.3.489 component_id_1
3.3.490 component_id_2
3.3.491 component_id_3
A Signal Descriptions
A.1 Signals list
B Revisions
B.1 Revisions

Release information

Document History
Issue Date Confidentiality Change
0000-00 10 May 2016 Non-Confidential First release for r0p0
0000-01 30 October 2016 Non-Confidential Second release for r0p0

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