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Configures the read-to-read timing parameter. This determines the READ to READ command delay applied between reads to the same chip, other bank group (t_rtr_s), same chip, same bank group (t_rtr_l), different chip-selects (t_rtr_cs), and same chip, different logical rank(t_rtr_dlr). Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_rtr_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.