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Configures the t_wdqlvl_ww timing parameter. Specifies the cycle delay between training commands. Also specifies the minimum delay between the last training command and deassertingdfi_wrlvl_en on observing dfi_wdqlvl_resp. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_wdqlvl_ww_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.