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Configures the read-to-write timing parameter. This determines the READ to WRITE command delay applied between issued commands to the same chip, other bank group (t_rtw_s), same chip, same bank group (t_trw_l), and other chip-selects (t_rtw_cs). Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_rtw_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.