|Non-Confidential||PDF version||ARM 100568_0000_01_en|
|Home > Programmers Model > Register descriptions > t_esrck_next|
Configures the delay between entering self-refresh and disabling the DRAM clock. This parameter is applied when stopping the clock when in self-refresh and when in a maximum power-down state. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_esrck_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.