3.3.131 t_esrck_next

Configures the delay between entering self-refresh and disabling the DRAM clock. This parameter is applied when stopping the clock when in self-refresh and when in a maximum power-down state. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The t_esrck_next register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x268

Type

Read-write

Reset

0x00000005

Width

32

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