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Determines the Mode Register command to use to place the DRAM into a training mode for read training, when enabled by the rdlvl_control register. See the PHY interface section of the Integration Manual for more information on PHY training. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The rdlvl_mrs_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.