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ARM® CoreLink™ DMC-620 Dynamic Memory Controller Technical Reference ManualRevision r0p0
Home > Programmers Model > Register descriptions > pmu_clk_counter_1_mask_31_00

3.3.324 pmu_clk_counter_1_mask_31_00

Masks PMU payload information. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The pmu_clk_counter_1_mask_31_00 register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0xB78
Type

Read-write
Reset

0x00000000
Width

32
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