| Non-Confidential |  PDF version | ARM 100568_0000_01_en | ||
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| Home > Programmers Model > Register descriptions > decode_control_now | ||||
| Non-Confidential | PDF version | ARM 100568_0000_01_en | ||
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| Home > Programmers Model > Register descriptions > decode_control_now | ||||
Configures how the DRAM address is decoded from the system address. The DRAM address consists of the rank, cid, bank, row, and the column address. Note: Order fields must be unique, ie. row_order != bank_order != rank_order. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG or LOW-POWER states.
The decode_control_now register characteristics are:
There are no usage constraints.
There is only one DMC configuration.
| Offset |
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| Type | Read-only |
| Reset |
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| Width | 32 |
| Non-Confidential | PDF version | ARM 100568_0000_01_en |
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