3.3.476 wdqlvl_vrefdq_train_mrs_now

Determines the Mode Register command to use to place the DRAM into a VrefDQ training mode as part of WrDQ training, when enabled by the wdqlvl_control register. You enable this function with the wdqlvl_control Register. See the PHY training interface section of the Integration Manual for more information. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.

The wdqlvl_vrefdq_train_mrs_now register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x1624

Type

Read-only

Reset

0x00000000

Width

32

Non-ConfidentialPDF file icon PDF versionARM 100568_0000_01_en
Copyright © 2016 ARM Limited or its affiliates. All rights reserved.