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| Home > Programmers Model > Register descriptions > wdqlvl_vrefdq_train_mrs_now | ||||
| Non-Confidential | PDF version | ARM 100568_0000_01_en | ||
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| Home > Programmers Model > Register descriptions > wdqlvl_vrefdq_train_mrs_now | ||||
Determines the Mode Register command to use to place the DRAM into a VrefDQ training mode as part of WrDQ training, when enabled by the wdqlvl_control register. You enable this function with the wdqlvl_control Register. See the PHY training interface section of the Integration Manual for more information. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
The wdqlvl_vrefdq_train_mrs_now register characteristics are:
There are no usage constraints.
There is only one DMC configuration.
| Offset |
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| Type | Read-only |
| Reset |
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| Width | 32 |
| Non-Confidential | PDF version | ARM 100568_0000_01_en |
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