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Configures the t_rdlvl_rr timing parameter. This specifies the cycle delay between training commands. It also specifies the minimum delay between the last training command and deasserting dfi_rdlvl_en after observing dfi_rdlvl_resp. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_rdlvl_rr_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.