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Configures the t_wrlvl_en timing parameter. Specifies the cycle delay between asserting ODT for training and asserting dfi_wrlvl_en, the delay between asserting dfi_wrlvl_en and the first training command, the delay between deasserting dfi_wrlvl_en and de-asserting ODT, and deasserting ODT to any subsequent command. It is also used between ODT transitions and refreshes generated during training. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_wrlvl_en_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.