|Home > Programmers model > Register summary > t_db_train_resp_next|
Configures the t_db_train_resp timing parameter for DB-DRAM Training. With DFI4.0 PHY this register is specified to define the cycle delay between DFI read command and when the response is valid on the dfi_db_train_resp. However this register can also be configured in DFI3.1 mode (optional: in absence of dfi_rddata_valid) to define the delay between DFI read command and when the response is valid on the dfi_rddata. This must include the whole round trip time including the board delays, take a look at DFI4.0 spec for details. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_db_train_resp_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.