|Home > Programmers model > Register summary > t_wrlvl_ww_next|
Configures the t_wrlvl_ww timing parameter. Specifies the cycle delay between training commands. Also specifies the minimum delay between the last training command and de-asserting dfi_wrlvl_en on observing dfi_wrlvl_resp. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_wrlvl_ww_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.