|Home > Programmers model > Register summary > t_clock_control_now|
Configures the enter DRAM clock disable timing parameter. This parameter is applied between stopping the clock when idle, or when in a power-down state, and any subsequent commands to the same rank. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
The t_clock_control_now register characteristics are:
There are no usage constraints.
There is only one DMC configuration.