3.3.438 t_clock_control_now

Configures the enter DRAM clock disable timing parameter. This parameter is applied between stopping the clock when idle, or when in a power-down state, and any subsequent commands to the same rank. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.

The t_clock_control_now register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x1250

Type

Read-only

Reset

0x00000505

Width

32

Non-ConfidentialPDF file icon PDF version100568_0100_00_en
Copyright © 2016, 2017 Arm Limited (or its affiliates). All rights reserved.