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Configures the write-to-read timing parameter, for both same chip, other bank group (tWTR_s), same chip, same bank group (t_WTR_l), and alternate chip (tWTR_cs).Note: This timing parameter is derived differently than indicated in the DRAM timing specification: It is derived from the start of the WRITE command as opposed to the end of the data burst. To program this parameter correctly the following formula should be used: t_wtr(dmc) = CWL+WBL/2+tWR(DRAM) Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_wtr_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.