3.3.5 decode_control_next

Configures how the DRAM address is decoded from the system address. The DRAM address consists of the rank, cid, bank, row, and the column address. Note: Order fields must be unique, ie. row_order != bank_order != rank_order. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The decode_control_next register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x014

Type

Read-write

Reset

0x001A3000

Width

32

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