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Configures the write-to-write timing parameter for same chip, other bank group (t_wtw_s), same chip, same bank group (t_wtw_l), alternate chip (t_wtw_cs) writes, same chip, different logical rank(t_wtw_dlr). Note: these must take into account CRC timing requirements. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_wtw_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.