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Configures the tWR timing parameter. This determines the write recovery time and is used as the delay applied between the issue of a WRITE command and subsequent commands, other than WRITEs, to the same bank. Note: This timing parameter is derived differently than indicated in the DRAM timing specification: It is derived from the start of the WRITE command as opposed to the end of the data burst. To program this parameter correctly the following formula should be used: t_wr(dmc) = CWL+4+tWR(from dram data sheet). CWL should account for write CRC if enabled. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
The t_wr_now register characteristics are:
There are no usage constraints.
There is only one DMC configuration.