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| Home > Programmers model > Register summary > t_esrck_now | ||||
| Non-Confidential | PDF version | 100568_0100_00_en | ||
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| Home > Programmers model > Register summary > t_esrck_now | ||||
Configures the delay between entering self-refresh and disabling the DRAM clock. This parameter is applied when stopping the clock when in self-refresh and when in a maximum power-down state. Access restrictions: RO Can be read from when in ALL states. Cannot be written to and only updated when in CONFIG, LOW-POWER or PAUSED states.
The t_esrck_now register characteristics are:
There are no usage constraints.
There is only one DMC configuration.
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| Type | Read-only |
| Reset |
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| Width | 32 |
| Non-Confidential | PDF version | 100568_0100_00_en |
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