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Controls the DQ mapping compensation applied for CRC calculation. For each nibble of the DQ bus, the DIMM SPD defines a DQ Map Index to define the bit connectivity to each rank. Program the DQ Map Index retrieved from the SPD for DIMM Check Bits bus into this register in the DMC for correct CRC operation. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The dq_map_control_71_64_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.