2.1 About the functions

This section gives a brief description of all the functions of the DMC-620.

The following figure shows a block diagram of the functions of the DMC-620. The colors show the different categories of functions:

Figure 2-1 DMC functional block diagram
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System Interface

The DMC-620 interfaces to the rest of the SoC through the System interface. This interface connects to a CHI Slave Node (SN-F) interface. For any attempted accesses that the system makes outside of the programmed address range, the System interface responds with a Non-data Error (NDERR) response. Depending on how you program the DMC-620, it converts the system access information to the correct rank, bank, column, and row access of the external SDRAM. The System interface supports TrustZone® features to regulate Secure and Non-secure accesses to both Secure and Non-secure regions of memory.

The DMC monitors queue occupancies and dictates whether system requests of any given QoS are accepted. Prefetched and Dynamic P-Credit requests are allocated based on a threshold setting, which is derived from register settings.

Note:

There is no support for exclusive access in the DMC because the CoreLink™ CCN-5xx and CMN-6xx products support exclusive access requests in the Home Node (HN-F).

Memory channel

Through this interface, the DMC-620 conducts data transactions with the SDRAM and regulates the power consumption of the SDRAM. The DMC-620 uses the ECC information that it receives from the SDRAM to maximize the reliability from these devices.

Programming interface

Through this interface, a master in the system programs the DMC-620. You can define the Secure and Non-secure regions of external memory. You can also define how the DMC-620 addresses the external memory from the address that the system provides on its System interface. You can also make direct accesses to the SDRAM, for example to initialize it.

QoS engine

The DMC-620 provides controls to enable you to adjust its arbitration scheme for your system to maximize the availability of your external memory devices. It provides buffers to reorder system transaction requests. It uses an advanced scheduling algorithm to ensure that traffic going to one memory bank causes minimal disruption to traffic going to a different memory bank. It also schedules transaction requests according to the availability of the destination memory bank. For system access requests to different available memory banks, the DMC-620 arbitrates these requests using the QoS priority initially, and then the temporal priority. The memory access requests all compete for control of the external SDRAM bus and SDRAM bank.

RAS

RAS features include support for the following:

  • V8.2 RAS Extension compliant.
  • Supports end-to-end RAS protection, data poisoning, and deferment.
  • SECDED ECC and symbol-based ECC for external DRAM. The symbol-based ECC performs quad-symbol correct and multi-symbol detect.
  • SECDED ECC of on-chip SRAM buffers within the DMC-620.
  • An automated retry of failed read transactions.
  • Write-back of corrected errors.
  • To improve containment of faults, the DMC-620 supports:
    • Link error protection for the memory interface, including automated hardware recovery for system memory access, training, and other hardware operations.
    • Programmable data scrubbing. The DMC-620 periodically detects and corrects data errors in the memory autonomously.
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