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The DMC-620 normally operates as one synchronous clock domain between the interconnect and the external DDR interface. However, the Programming interface can operate asynchronously to this.
This section shows the clock and reset signals that the DMC-620 requires.
The DMC-620 has three clock inputs:
Resets must be applied for a minimum duration of 16 clock cycles for each clock domain.
There are two reset inputs. RESETn resets both clk and the clkdiv2 registers and PRESETn resets the pclk registers. The pclk domain must be out of reset before the clk and clkdiv2 domains.