2.2 Clocking and resets

The DMC-620 normally operates as one synchronous clock domain between the interconnect and the external DDR interface. However, the Programming interface can operate asynchronously to this.

This section shows the clock and reset signals that the DMC-620 requires.


The DMC-620 has three clock inputs:

clk is the main DMC clock that runs at SDRAM clock frequency. It must run synchronous to, and at the same frequency, as the CHI interface. If the CHI interconnect is not running at SDRAM clock frequency, then an asynchronous bridge such as the CCN Device Source Synchronous Bridge (DSSB) must be used.
This clock runs the DFI interface and connects to both the DMC and the PHY. It must be edge synchronous to clk, and run at half the clk frequency.
pclk can run asynchronously to clk and clkdiv2.
Figure 2-2 SoC hierarchy
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Resets must be applied for a minimum duration of 16 clock cycles for each clock domain.

There are two reset inputs. RESETn resets both clk and the clkdiv2 registers and PRESETn resets the pclk registers. The pclk domain must be out of reset before the clk and clkdiv2 domains.


  • To assert any DMC-620 reset signal, you must set it LOW.
  • To perform a DMC-620 reset, you must assert both reset signals.
Non-ConfidentialPDF file icon PDF version100568_0100_00_en
Copyright © 2016, 2017 Arm Limited (or its affiliates). All rights reserved.