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Configures the t_rdlvl_en timing parameter. This specifies the cycle delay between asserting dfi_rdlvl_en and the first training command, and also the cycle delay between deasserting dfi_rdlvl_en and performing any subsequent command. It also specifies the minimum delay between training commands and refreshes during training. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The t_rdlvl_en_next register characteristics are:
There are no usage constraints.
There is only one DMC configuration.