A.1 Signals list

DMC signals list that excludes bus interface signals. The bus interface signals are defined by their own bus protocol standard.

The following table shows the Primary clock and reset signals bus list of the DMC.

Table A-1 DMC Primary clock and reset signals list

Name Width Description
clk Primary DMC clock
resetn Primary DMC reset

The following table shows the Divided Primary DMC clock. Edge Synchronous, half the frequency of clk bus list of the DMC.

Table A-2 DMC Divided Primary DMC clock. Edge Synchronous, half the frequency of clk list

Name Width Description
clkdiv2 Primary DMC clock. Edge Synchronous, half the frequency of clk
resetn Primary DMC reset

The following table shows the APB clock and reset signals bus list of the DMC.

Table A-3 DMC APB clock and reset signals list

Name Width Description
pclk APB clock
presetn APB reset

The following table shows the APB Interface bus list of the DMC.

Table A-4 DMC APB Interface list

Name Width Description
paddr 32 APB address
psel APB select
penable APB enable
pwrite APB write
pwdata 32 APB write data
pready APB ready
prdata 32 APB read data
pslverr APB error signal

The following table shows the DFI Interface bus list of the DMC.

Table A-5 DMC DFI Interface list

Name Width Description
dfi_address_p0 18 Address to DDR3 PHY
dfi_address_p1 18 Address to DDR3 PHY
dfi_bank_p0 3 Bank Address to PHY
dfi_bank_p1 3 Bank Address to PHY
dfi_ras_n_p0 1 Row address strobe to PHY
dfi_ras_n_p1 1 Row address strobe to PHY
dfi_cas_n_p0 1 Column address strobe to PHY
dfi_cas_n_p1 1 Column address strobe to PHY
dfi_we_n_p0 1 Write enable to PHY
dfi_we_n_p1 1 Write enable to PHY
dfi_cs_p0 MEMORY_CHIP_SELECTS Chip-select to PHY
dfi_cs_p1 MEMORY_CHIP_SELECTS Chip-select to PHY
dfi_act_n_p0 1 Activate to PHY
dfi_act_n_p1 1 Activate to PHY
dfi_bg_p0 2 Bank group address to PHY
dfi_bg_p1 2 Bank group address to PHY
dfi_cid_p0 3 Chip ID to PHY
dfi_cid_p1 3 Chip ID to PHY
dfi_cke_p0 MEMORY_CHIP_SELECTS Clock enable to PHY
dfi_cke_p1 MEMORY_CHIP_SELECTS Clock enable to PHY
dfi_odt_p0 MEMORY_CHIP_SELECTS On Die Termination to PHY
dfi_odt_p1 MEMORY_CHIP_SELECTS On Die Termination to PHY
dfi_reset_n_p0 MEMORY_CHIP_SELECTS Reset to PHY
dfi_reset_n_p1 MEMORY_CHIP_SELECTS Reset to PHY
dfi_parity_in_p0 1 Command parity to PHY
dfi_parity_in_p1 1 Command parity to PHY
dfi_wrdata_en_p0 (DFI_DATA_SLICES) Write data enable PHY
dfi_wrdata_en_p1 (DFI_DATA_SLICES) Write data enable PHY
dfi_wrdata_p0 (DFI_DATA_BITS/2) Write data to PHY
dfi_wrdata_p1 (DFI_DATA_BITS/2) Write data to PHY
dfi_wrdata_cs_p0 MEMORY_CHIP_SELECTS Write Data Path Chip-select to PHY
dfi_wrdata_cs_p1 MEMORY_CHIP_SELECTS Write Data Path Chip-select to PHY
dfi_wrdata_mask_p0 (DFI_DATA_BYTES/2) Write data mask PHY
dfi_wrdata_mask_p1 (DFI_DATA_BYTES/2) Write data mask PHY
dfi_rddata_en_p0 (DFI_DATA_SLICES) Enable for read data
dfi_rddata_en_p1 (DFI_DATA_SLICES) Enable for read data
dfi_rddata_p0 (DFI_DATA_BITS/2) Read data input from PHY
dfi_rddata_p1 (DFI_DATA_BITS/2) Read data input from PHY
dfi_rddata_dbi_p0 (DFI_DATA_SLICES*2) Read Data DBI. This signal is sent with dfi_rddata bus indicating DBI functionality. If not used this signal must be tied to 'b1.
dfi_rddata_dbi_p1 (DFI_DATA_SLICES*2) Read Data DBI. This signal is sent with dfi_rddata bus indicating DBI functionality. If not used this signal must be tied to 'b1.
dfi_rddata_valid_p0 (DFI_DATA_SLICES) Indicates read data valid
dfi_rddata_valid_p1 (DFI_DATA_SLICES) Indicates read data valid
dfi_rddata_cs_p0 MEMORY_CHIP_SELECTS Read Data Path Chip-select to PHY
dfi_rddata_cs_p1 MEMORY_CHIP_SELECTS Read Data Path Chip-select to PHY
dfi_ctrlupd_req 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_ctrlupd_ack 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_phyupd_req 1 DFI PHY-initiated update request
dfi_phyupd_ack 1 DFI PHY-initiated update acknowledge
dfi_phyupd_type 2 DFI PHY-initiated update type
dfi_data_byte_disable (DFI_DATA_BYTES/2) This signal is part of DFI 4.0, see DFI specification for details.
dfi_dram_clk_disable MEMORY_CHIP_SELECTS DRAM clock disable to PHY
dfi_init_start 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_init_complete 1 Indicates PHY initialization complete
dfi_alert_n_p0 1 This signal is part of DFI 4.0, see JEDEC specification for details.
dfi_alert_n_p1 1 This signal is part of DFI 4.0, see JEDEC specification for details.
dfi_frequency 5 This signal is part of DFI 4.0, see DFI specification for details.
dfi_geardown_en 1 This signal is part of DFI 4.0 Geardown Interface.
dfi_err 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_err_info 4 This signal is part of DFI 4.0, see DFI specification for details.
dfi_disconnect_error 1 Provides Disconnect type if a disconnect occurs on training, update, or PHY-master interface. This signal is part of DFI 4.0 Disconnect Interface.
dfi_phymstr_req 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_phymstr_cs_state MEMORY_CHIP_SELECTS This signal is part of DFI 4.0, see DFI specification for details.
dfi_phymstr_state_sel 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_phymstr_type 2 This signal is part of DFI 4.0, see DFI specification for details.
dfi_phymstr_ack 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_phylvl_req_cs_n MEMORY_CHIP_SELECTS This signal is part of DFI 3.1, see DFI specification for details.
dfi_phylvl_ack_cs_n MEMORY_CHIP_SELECTS This signal is part of DFI 3.1, see DFI specification for details.
dfi_rdlvl_req DFI_DATA_SLICES DFI read data eye training request
dfi_rdlvl_cs MEMORY_CHIP_SELECTS DFI read data eye training request target chip-select
dfi_rdlvl_en DFI_DATA_SLICES DFI read data eye training enable
dfi_rdlvl_resp (DFI_DATA_SLICES*2) DFI read data eye training response
dfi_rdlvl_done DFI_DATA_SLICES DFI Read data eye training done
dfi_rdlvl_gate_req DFI_DATA_SLICES DFI read gate training request
dfi_rdlvl_gate_cs MEMORY_CHIP_SELECTS DFI read gate training request target chip-select
dfi_rdlvl_gate_en DFI_DATA_SLICES DFI read gate training enable
dfi_wrlvl_req DFI_DATA_SLICES DFI write leveling training request
dfi_wrlvl_cs MEMORY_CHIP_SELECTS DFI write leveling training request target chip-select
dfi_wrlvl_en DFI_DATA_SLICES DFI write leveling training enable
dfi_wrlvl_strobe_p0 DFI_DATA_SLICES DFI write leveling training strobe
dfi_wrlvl_strobe_p1 DFI_DATA_SLICES DFI write leveling training strobe
dfi_wrlvl_resp DFI_DATA_SLICES DFI write leveling training response
dfi_wdqlvl_req DFI_DATA_SLICES DFI Write-DQ leveling training request
dfi_wdqlvl_cs MEMORY_CHIP_SELECTS DFI Write-DQ leveling training request target chip-select
dfi_wdqlvl_en DFI_DATA_SLICES DFI Write-DQ leveling training enable
dfi_wdqlvl_result DFI_DATA_SLICES DFI Write-DQ leveling training result
dfi_wdqlvl_done DFI_DATA_SLICES DFI Write-DQ leveling training done
dfi_wdqlvl_resp (DFI_DATA_SLICES*2) DFI Write-DQ leveling training response
dfi_lvl_pattern 4 This signal is part of DFI 4.0, see DFI specification for details.
dfi_lvl_periodic 1 This signal is part of DFI 4.0, see DFI specification for details.
dfi_db_train_en DFI_DATA_SLICES Enable for DB-DRAM Training. This signal is part of DFI 4.0 DB-DRAM Training.
dfi_db_train_resp_w0 (DFI_DATA_SLICES*DFI_SLICE_WIDTH/4) Response data for DB-DRAM Training. This signal is part of DFI 4.0.
dfi_db_train_resp_w1 (DFI_DATA_SLICES*DFI_SLICE_WIDTH/4) Response data for DB-DRAM Training. This signal is part of DFI 4.0.
dfi_lp_ctrl_req 1 DFI command low-power request
dfi_lp_data_req 1 DFI data low-power request
dfi_lp_wakeup 4 DFI command low-power PHY wakeup allowance
dfi_lp_ack 1 DFI command low-power acknowledge

The following table shows the Q-Channel Interface for DMC bus list of the DMC.

Table A-6 DMC Q-Channel Interface for DMC list

Name Width Description
qreqn 1 Request from the external clock controller to prepare to stop the clock
qacceptn 1 Positive acknowledgement after receiving QREQn assertion indicating that the DMC has completed preparation to stop the clocks and that the external clock controller can stop the clock
qdeny 1 Negative acknowledgement after receiving QREQn assertion indicating that the DMC has refused the request from the external clock controller to prepare to stop the clock
qactive 1 Indication that the DMC is active

The following table shows the Q-Channel Interface for APB interface bus list of the DMC.

Table A-7 DMC Q-Channel Interface for APB interface list

Name Width Description
qreqn_apb 1 Request from the external clock controller to prepare to stop the clock
qacceptn_apb 1 Positive acknowledgement after receiving QREQn assertion indicating that the APB interface has completed preparation to stop the clocks and that the external clock controller can stop the clock
qdeny_apb 1 Negative acknowledgement after receiving QREQn assertion indicating that the APB interface has refused the request from the external clock controller to prepare to stop the clock
qactive_apb 1 Indication that the APB interface is active

The following table shows the Clock Frequency Change Interface bus list of the DMC.

Table A-8 DMC Clock Frequency Change Interface list

Name Width Description
cc_frequency 5 Used to indicate new frequency as part of frequency change protocol
cc_freq_change_req 1 Signals to an external clock control that the clock frequency can be updated
cc_freq_change_ack 1 Signals to the DMC from an external clock control that the clock frequency has been updated

The following table shows the Clock Frequency Change Interface bus list of the DMC.

Table A-9 DMC Clock Frequency Change Interface list

Name Width Description
dfi_frequency 5 Used to indicate new frequency as part of frequency change protocol
dfi_freq_change_req 1 Signals to an external clock control that the clock frequency can be updated
dfi_freq_change_ack 1 Signals to the DMC from an external clock control that the clock frequency has been updated

The following table shows the Abort Interface bus list of the DMC.

Table A-10 DMC Abort Interface list

Name Width Description
abort_req 1 An input to abort retries in the face of DFI link errors.
abort_err_type 1 Abort Error Type as a payload to abort_req.
abort_ack 1 An output to acknowledge that the DMC has completed outstanding transactions as a result of an abort.

The following table shows the Memory BIST interface bus list of the DMC.

Table A-11 DMC Memory BIST interface list

Name Width Description
mbistresetn 1 MBIST reset. Active low.
mbistreq 1 MBIST request
mbistack 1 MBIST acknowledge
mbistwriteen 1 MBIST write enable
mbistreaden 1 MBIST read enable
mbistaddr MAX_TID_BITS MBIST address
mbistarray 4 MBIST array selection
mbistcfg 1 MBIST Configuration
mbistindata 154 MBIST write data
mbistoutdata 154 MBIST read data

The following table shows the DFT interface bus list of the DMC.

Table A-12 DMC DFT interface list

Name Width Description
DFTCLKCGEN 1 DFT clock gate override
DFTRSTDISABLE 2 DFT reset synchronizer disable
DFTRAMHOLD 1 DFT on-chip RAM hold
DFTMCPHOLD 1 DFT multicycle path hold

The following table shows the user-defined inputs bus list of the DMC.

Table A-13 DMC user-defined inputs list

Name Width Description
user_status 32 User-defined inputs

The following table shows the user-defined outputs bus list of the DMC.

Table A-14 DMC user-defined outputs list

Name Width Description
user_config0 32 User-defined outputs

The following table shows the user-defined outputs bus list of the DMC.

Table A-15 DMC user-defined outputs list

Name Width Description
user_config1 32 User-defined outputs

The following table shows the user-defined outputs bus list of the DMC.

Table A-16 DMC user-defined outputs list

Name Width Description
user_config2 32 User-defined outputs

The following table shows the user-defined outputs bus list of the DMC.

Table A-17 DMC user-defined outputs list

Name Width Description
user_config3 32 User-defined outputs

The following table shows the Direct command event trigger inputs bus list of the DMC.

Table A-18 DMC Direct command event trigger inputs list

Name Width Description
direct_cmd_event_in 4 Direct command event trigger inputs

The following table shows the Direct command event triggered outputs bus list of the DMC.

Table A-19 DMC Direct command event triggered outputs list

Name Width Description
direct_cmd_event_out 4 Direct command event triggered outputs

The following table shows the memory_type bus list of the DMC.

Table A-20 DMC memory_type list

Name Width Description
memory_type 3 An external output of the value of the memory_type register bitfield.

The following table shows the Tie-off value to set the value of CMOD in the periph_id_3 bitfield bus list of the DMC.

Table A-21 DMC Tie-off value to set the value of CMOD in the periph_id_3 bitfield list

Name Width Description
user_periph_id_3 8 Tie-off value to set the value of CMOD in the periph_id_3 bitfield

The following table shows the Tie-off value for reset of register bitfield t_rddata_en_diff bus list of the DMC.

Table A-22 DMC Tie-off value for reset of register bitfield t_rddata_en_diff list

Name Width Description
t_rddata_en_diff_tie_off 6 Tie-off value for reset of register bitfield t_rddata_en_diff

The following table shows the Tie-off value for reset of register bitfield t_phyrdcslat bus list of the DMC.

Table A-23 DMC Tie-off value for reset of register bitfield t_phyrdcslat list

Name Width Description
t_phyrdcslat_tie_off 5 Tie-off value for reset of register bitfield t_phyrdcslat

The following table shows the Tie-off value for reset of register bitfield t_phyrdlat bus list of the DMC.

Table A-24 DMC Tie-off value for reset of register bitfield t_phyrdlat list

Name Width Description
t_phyrdlat_tie_off 7 Tie-off value for reset of register bitfield t_phyrdlat

The following table shows the Tie-off value for reset of register bitfield t_phywrlat_diff bus list of the DMC.

Table A-25 DMC Tie-off value for reset of register bitfield t_phywrlat_diff list

Name Width Description
t_phywrlat_diff_tie_off 5 Tie-off value for reset of register bitfield t_phywrlat_diff

The following table shows the Tie-off value for reset of register bitfield t_phywrcslat bus list of the DMC.

Table A-26 DMC Tie-off value for reset of register bitfield t_phywrcslat list

Name Width Description
t_phywrcslat_tie_off 5 Tie-off value for reset of register bitfield t_phywrcslat

The following table shows the Tie-off value for reset of register bitfield t_phywrdata bus list of the DMC.

Table A-27 DMC Tie-off value for reset of register bitfield t_phywrdata list

Name Width Description
t_phywrdata_tie_off 1 Tie-off value for reset of register bitfield t_phywrdata

The following table shows the Tie-off value for reset of register bitfield refresh_dur_rdlvl bus list of the DMC.

Table A-28 DMC Tie-off value for reset of register bitfield refresh_dur_rdlvl list

Name Width Description
refresh_dur_rdlvl_tie_off 1 Tie-off value for reset of register bitfield refresh_dur_rdlvl

The following table shows the Tie-off value for reset of register bitfield t_rdlvl_en bus list of the DMC.

Table A-29 DMC Tie-off value for reset of register bitfield t_rdlvl_en list

Name Width Description
t_rdlvl_en_tie_off 6 Tie-off value for reset of register bitfield t_rdlvl_en

The following table shows the Tie-off value for reset of register bitfield t_rdlvl_rr bus list of the DMC.

Table A-30 DMC Tie-off value for reset of register bitfield t_rdlvl_rr list

Name Width Description
t_rdlvl_rr_tie_off 10 Tie-off value for reset of register bitfield t_rdlvl_rr

The following table shows the Tie-off value for reset of register bitfield refresh_dur_wrlvl bus list of the DMC.

Table A-31 DMC Tie-off value for reset of register bitfield refresh_dur_wrlvl list

Name Width Description
refresh_dur_wrlvl_tie_off 1 Tie-off value for reset of register bitfield refresh_dur_wrlvl

The following table shows the Tie-off value for reset of register bitfield t_wrlvl_en bus list of the DMC.

Table A-32 DMC Tie-off value for reset of register bitfield t_wrlvl_en list

Name Width Description
t_wrlvl_en_tie_off 6 Tie-off value for reset of register bitfield t_wrlvl_en

The following table shows the Tie-off value for reset of register bitfield t_wrlvl_ww bus list of the DMC.

Table A-33 DMC Tie-off value for reset of register bitfield t_wrlvl_ww list

Name Width Description
t_wrlvl_ww_tie_off 10 Tie-off value for reset of register bitfield t_wrlvl_ww

The following table shows the Tie-off value for reset of register bitfield refresh_dur_wrlvl bus list of the DMC.

Table A-34 DMC Tie-off value for reset of register bitfield refresh_dur_wrlvl list

Name Width Description
refresh_dur_wdqlvl_tie_off 1 Tie-off value for reset of register bitfield refresh_dur_wrlvl

The following table shows the Tie-off value for reset of register bitfield t_wdqlvl_ww bus list of the DMC.

Table A-35 DMC Tie-off value for reset of register bitfield t_wdqlvl_ww list

Name Width Description
t_wdqlvl_ww_tie_off 10 Tie-off value for reset of register bitfield t_wdqlvl_ww

The following table shows the Tie-off value for reset of register bitfield t_wdqlvl_rw bus list of the DMC.

Table A-36 DMC Tie-off value for reset of register bitfield t_wdqlvl_rw list

Name Width Description
t_wdqlvl_rw_tie_off 10 Tie-off value for reset of register bitfield t_wdqlvl_rw

The following table shows the Tie-off value for reset of register bitfield t_wdqlvl_en bus list of the DMC.

Table A-37 DMC Tie-off value for reset of register bitfield t_wdqlvl_en list

Name Width Description
t_wdqlvl_en_tie_off 6 Tie-off value for reset of register bitfield t_wdqlvl_en

The following table shows the Tie-off value for reset of register bitfield refresh_dur_phymstr bus list of the DMC.

Table A-38 DMC Tie-off value for reset of register bitfield refresh_dur_phymstr list

Name Width Description
refresh_dur_phymstr_tie_off 1 Tie-off value for reset of register bitfield refresh_dur_phymstr

The following table shows the Tie-off value for reset of register bitfield t_db_train_resp bus list of the DMC.

Table A-39 DMC Tie-off value for reset of register bitfield t_db_train_resp list

Name Width Description
t_db_train_resp_tie_off 7 Tie-off value for reset of register bitfield t_db_train_resp

The following table shows the Tie-off value for reset of register bitfield t_lpresp bus list of the DMC.

Table A-40 DMC Tie-off value for reset of register bitfield t_lpresp list

Name Width Description
t_lpresp_tie_off 6 Tie-off value for reset of register bitfield t_lpresp

The following table shows the Tie-off value for reset of register bitfield user_config0 bus list of the DMC.

Table A-41 DMC Tie-off value for reset of register bitfield user_config0 list

Name Width Description
user_config0_tie_off 32 Tie-off value for reset of register bitfield user_config0

The following table shows the Tie-off value for reset of register bitfield user_config1 bus list of the DMC.

Table A-42 DMC Tie-off value for reset of register bitfield user_config1 list

Name Width Description
user_config1_tie_off 32 Tie-off value for reset of register bitfield user_config1

The following table shows the Tie-off value for reset of register bitfield user_config2 bus list of the DMC.

Table A-43 DMC Tie-off value for reset of register bitfield user_config2 list

Name Width Description
user_config2_tie_off 32 Tie-off value for reset of register bitfield user_config2

The following table shows the Tie-off value for reset of register bitfield user_config3 bus list of the DMC.

Table A-44 DMC Tie-off value for reset of register bitfield user_config3 list

Name Width Description
user_config3_tie_off 32 Tie-off value for reset of register bitfield user_config3

The following table shows the Tie-off value to set the physical node ID of the DMC bus list of the DMC.

Table A-45 DMC Tie-off value to set the physical node ID of the DMC list

Name Width Description
system_id CHI_RSP_FLIT_SRCID_WIDTH Tie-off value to set the physical node ID of the DMC

The following table shows the Tie off value to specify the concatenated physical node IDs of up to SYSTEM_REQUESTORS Home Nodes that are permitted to access the DMC. SYSTEM_REQUESTORS is 8 when configured as DMC_CHIB==0, and is 32 when configured as DMC_CHIB==1. Bus list of the DMC.

Table A-46 DMC Tie off value to specify the concatenated physical node IDs list

Name Width Description
home_node_id (CHI_REQ_FLIT_SRCID_WIDTH*SYSTEM_REQUESTORS) Tie off value to specify the concatenated physical node IDs of the requestors that are permitted to access the DMC

The following table shows the Tie-off value to set the value for dfi_lvl_periodic when a dfi_rdlvl_req is occurring bus list of the DMC.

Table A-47 DMC Tie-off value to set the value for dfi_lvl_periodic when a dfi_rdlvl_req is occurring list

Name Width Description
dfi_rdlvl_periodic 1 Tie-off value to set the value for dfi_lvl_periodic when a dfi_rdlvl_req is occurring

The following table shows the Tie-off value to set the value for dfi_lvl_periodic when a dfi_rdlvl_gate_req is occurring bus list of the DMC.

Table A-48 DMC Tie-off value to set the value for dfi_lvl_periodic when a dfi_rdlvl_gate_req is occurring list

Name Width Description
dfi_rdlvl_gate_periodic 1 Tie-off value to set the value for dfi_lvl_periodic when a dfi_rdlvl_gate_req is occurring

The following table shows the Tie-off value to set the value for dfi_lvl_periodic when a dfi_wrlvl_req is occurring bus list of the DMC.

Table A-49 DMC Tie-off value to set the value for dfi_lvl_periodic when a dfi_wrlvl_req is occurring list

Name Width Description
dfi_wrlvl_periodic 1 Tie-off value to set the value for dfi_lvl_periodic when a dfi_wrlvl_req is occurring

The following table shows the Tie-off value to set the value for dfi_lvl_periodic when a dfi_wdqlvl_req is occurring bus list of the DMC.

Table A-50 DMC Tie-off value to set the value for dfi_lvl_periodic when a dfi_wdqlvl_req is occurring list

Name Width Description
dfi_wdqlvl_periodic 1 Tie-off value to set the value for dfi_lvl_periodic when a dfi_wdqlvl_req is occurring

The following table shows the interrupt signal list of the DMC.

Table A-51 DMC interrupts list

Name Width Description
er_int 1 The DMC has detected an uncorrectable error or previously poisoned data that cannot be deferred
cfh_int 1 The number of correctable errors detected by the DMC has overflowed an error counter
fh_int 1 The DMC has detected a new (non-poisoned) data failure that cannot be corrected, but might be able to be deferred
failed_access_int 1 The DMC has detected a system request that has failed a permissions check
failed_prog_int 1 The DMC has detected a programming request that is not permitted
link_err_int 1 The DRAM interface has suffered from a link failure and a recovery attempt has begun
temperature_event_int 1 The DMC has detected a temperature event signaled by the DRAM, either directly, or if a temperature delta has been observed through automated polling of the temperature sensor
arch_fsm_int 1 The DMC has detected a change in the architectural state
scrub_engine0_complete_int 1 The DMC scrub engine 0 has completed a scrub
scrub_engine1_complete_int 1 The DMC scrub engine 1 has completed a scrub
scrub_engine_behind_schedule_int 1 A DMC scrub engine is behind schedule
phy_request_int 1 The DMC has detected a PHY request
combined_int 1 A combined interrupt that is the logical OR of the other interrupts
failed_access_oflow 1 The DMC has detected a system request that has failed a permissions check and a previously detected assertion was not cleared
failed_prog_oflow 1 The DMC has detected a programming request that is not permitted and a previously detected assertion was not cleared
link_err_oflow 1 The DRAM interface has suffered from a link failure and a recovery attempt has begun and a previously detected assertion was not cleared
temperature_event_oflow 1 The DMC has detected a temperature event signaled by the DRAM, either directly, or if a temperature delta has been observed through automated polling of the temperature sensor and a previously detected assertion was not cleared
arch_fsm_oflow 1 The DMC has detected a change in the architectural state and a previously detected assertion was not cleared
scrub_engine0_complete_oflow 1 The DMC scrub engine 0 has completed a scrub and a previously detected assertion was not cleared
scrub_engine1_complete_oflow 1 The DMC scrub engine 1 has completed a scrub and a previously detected assertion was not cleared
scrub_engine_behind_schedule_oflow 1 A DMC scrub engine is behind schedule and a previously detected assertion was not cleared
phy_request_oflow 1 The DMC has detected a PHY request and a previously detected assertion was not cleared
combined_oflow 1 A combined interrupt that is the logical OR of the other interrupt overflows.
pmu_counter_oflow 1 An interrupt that indicates at least one PMU counter has overflowed
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