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Maps PHY training request from a physical chip select to DMC internal logical chip select. Requests which are mapped using this register are dfi_rdlvl_cs, dfi_rdlvl_gate_cs, dfi_wrlvl_cs, dfi_phylvl_req_cs_n and dfi_phymstr_cs_state. The default settings are a 1:1 logical to physical rank mapping. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.
The phy_request_cs_remap register characteristics are:
There are no usage constraints.
There is only one DMC configuration.