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Arm® CoreLink™ DMC-620 Dynamic Memory Controller Technical Reference ManualRevision r1p0
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3.3.223 err2addr1

Contains the physical CID and Rank broken out in the following way {[31:6] = Reserved, [5:3] = CID, [2:0] = Rank} Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The err2addr1 register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x79C
Type

Read-write
Reset

0x00000000
Width

32
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