3.3.304 pmu_clkdiv2_counter_5_control

Controls muxes, enables and other control bits for the PMU counters Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The pmu_clkdiv2_counter_5_control register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0xAE8

Type

Read-write

Reset

0x00000000

Width

32

Non-ConfidentialPDF file icon PDF version100568_0100_00_en
Copyright © 2016, 2017 Arm Limited (or its affiliates). All rights reserved.