3.3.127 t_clock_control_next

Configures the enter DRAM clock disable timing parameter. This parameter is applied between stopping the clock when idle, or when in a power-down state, and any subsequent commands to the same rank. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The t_clock_control_next register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x250

Type

Read-write

Reset

0x00000505

Width

32

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