3.3.104 phy_rdwrdata_cs_mask_31_00

Maps a logical rank to the physical rank phy_rd/wrdata_cs output pins. Using this register it is possible to map a logical rank to multiple phy_rdwrdata_cs output pins. The default settings are a 1:1 logical to physical rank mapping. Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The phy_rdwrdata_cs_mask_31_00 register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x1E0

Type

Read-write

Reset

0xF7FBFDFE

Width

32

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