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Arm® CoreLink™ DMC-620 Dynamic Memory Controller Technical Reference ManualRevision r1p0
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3.3.227 err2misc3

DRAM Uncorrectable Error Counters Access restrictions: RW Can be read from when in ALL states. Can be written to when in ALL states.

The err2misc3 register characteristics are:

Usage constraints

There are no usage constraints.

Configurations

There is only one DMC configuration.

Attributes
Offset

0x7AC
Type

Read-write
Reset

0x00000000
Width

32
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