Arm® Cortex®‑A76 Core Technical Reference Manual

Revision r3p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Typographic conventions
Timing diagrams
Signals
Additional reading
Feedback
Feedback on this product
Feedback on content
Part A Functional description
A1 Introduction
A1.1 About the core
A1.2 Features
A1.3 Implementation options
A1.4 Supported standards and specifications
A1.5 Test features
A1.6 Design tasks
A1.7 Product revisions
A2 Technical overview
A2.1 Components
A2.1.1 Instruction fetch
A2.1.2 Instruction decode
A2.1.3 Register rename
A2.1.4 Instruction issue
A2.1.5 Execution pipeline
A2.1.6 L1 data memory system
A2.1.7 L2 memory system
A2.2 Interfaces
A2.3 About system control
A2.4 About the Generic Timer
A3 Clocks, resets, and input synchronization
A3.1 About clocks, resets, and input synchronization
A3.2 Asynchronous interface
A4 Power management
A4.1 About power management
A4.2 Voltage domains
A4.3 Power domains
A4.4 Architectural clock gating modes
A4.4.1 Core Wait for Interrupt
A4.4.2 Core Wait for Event
A4.5 Power control
A4.6 Core power modes
A4.6.1 On
A4.6.2 Off
A4.6.3 Off (emulated)
A4.6.4 Core dynamic retention
A4.6.5 Debug recovery mode
A4.7 Encoding for power modes
A4.8 Power domain states for power modes
A4.9 Power up and down sequences
A4.10 Debug over powerdown
A5 Memory Management Unit
A5.1 About the MMU
A5.1.1 Main functions
A5.1.2 AArch64 behavior
A5.2 TLB organization
A5.2.1 Instruction L1 TLB
A5.2.2 Data L1 TLB
A5.2.3 L2 TLB
A5.3 TLB match process
A5.4 Translation table walks
A5.4.1 AArch64 behavior
A5.5 MMU memory accesses
A5.5.1 Configuring MMU accesses
A5.5.2 Descriptor hardware update
A5.6 Specific behaviors on aborts and memory attributes
A5.6.1 External aborts
A5.6.2 Mis-programming contiguous hints
A5.6.3 Memory attributes
A6 Level 1 memory system
A6.1 About the L1 memory system
A6.1.1 L1 instruction-side memory system
A6.1.2 L1 data-side memory system
A6.2 Cache behavior
A6.2.1 Instruction cache disabled behavior
A6.2.2 Instruction cache speculative memory accesses
A6.2.3 Data cache disabled behavior
A6.2.4 Data cache maintenance considerations
A6.2.5 Data cache coherency
A6.2.6 Write streaming mode
A6.3 L1 instruction memory system
A6.3.1 Program flow prediction
A6.4 L1 data memory system
A6.4.1 Memory system implementation
A6.4.2 Internal exclusive monitor
A6.5 Data prefetching
A6.6 Direct access to internal memory
A6.6.1 Encoding for L1 instruction cache tag, L1 instruction cache data, L1 BTB, L1 GHB, L1 TLB instruction, and BPIQ
A6.6.2 Encoding for L1 data cache tag, L1 data cache data, and L1 TLB data
A6.6.3 Encoding for the L2 unified cache
A6.6.4 Encoding for the L2 TLB
A7 Level 2 memory system
A7.1 About the L2 memory system
A7.2 About the L2 cache
A7.3 Support for memory types
A8 Reliability, Availability, and Serviceability (RAS)
A8.1 Cache ECC and parity
A8.2 Cache protection behavior
A8.3 Uncorrected errors and data poisoning
A8.4 RAS error types
A8.5 Error Synchronization Barrier
A8.6 Error recording
A8.7 Error injection
A9 Generic Interrupt Controller CPU interface
A9.1 About the Generic Interrupt Controller CPU interface
A9.2 Bypassing the CPU interface
A10 Advanced SIMD and floating-point support
A10.1 About the Advanced SIMD and floating-point support
A10.2 Accessing the feature identification registers
Part B Register descriptions
B1 AArch32 system registers
B1.1 AArch32 architectural system register summary
B2 AArch64 system registers
B2.1 AArch64 registers
B2.2 AArch64 architectural system register summary
B2.3 AArch64 implementation defined register summary
B2.4 AArch64 registers by functional group
B2.5 ACTLR_EL1, Auxiliary Control Register, EL1
B2.6 ACTLR_EL2, Auxiliary Control Register, EL2
B2.7 ACTLR_EL3, Auxiliary Control Register, EL3
B2.8 AFSR0_EL1, Auxiliary Fault Status Register 0, EL1
B2.9 AFSR0_EL2, Auxiliary Fault Status Register 0, EL2
B2.10 AFSR0_EL3, Auxiliary Fault Status Register 0, EL3
B2.11 AFSR1_EL1, Auxiliary Fault Status Register 1, EL1
B2.12 AFSR1_EL2, Auxiliary Fault Status Register 1, EL2
B2.13 AFSR1_EL3, Auxiliary Fault Status Register 1, EL3
B2.14 AIDR_EL1, Auxiliary ID Register, EL1
B2.15 AMAIR_EL1, Auxiliary Memory Attribute Indirection Register, EL1
B2.16 AMAIR_EL2, Auxiliary Memory Attribute Indirection Register, EL2
B2.17 AMAIR_EL3, Auxiliary Memory Attribute Indirection Register, EL3
B2.18 CCSIDR_EL1, Cache Size ID Register, EL1
B2.19 CLIDR_EL1, Cache Level ID Register, EL1
B2.20 CPACR_EL1, Architectural Feature Access Control Register, EL1
B2.21 CPTR_EL2, Architectural Feature Trap Register, EL2
B2.22 CPTR_EL3, Architectural Feature Trap Register, EL3
B2.23 CPUACTLR_EL1, CPU Auxiliary Control Register, EL1
B2.24 CPUACTLR2_EL1, CPU Auxiliary Control Register 2, EL1
B2.25 CPUCFR_EL1, CPU Configuration Register, EL1
B2.26 CPUECTLR_EL1, CPU Extended Control Register, EL1
B2.27 CPUPCR_EL3, CPU Private Control Register, EL3
B2.28 CPUPMR_EL3, CPU Private Mask Register, EL3
B2.29 CPUPOR_EL3, CPU Private Operation Register, EL3
B2.30 CPUPSELR_EL3, CPU Private Selection Register, EL3
B2.31 CPUPWRCTLR_EL1, Power Control Register, EL1
B2.32 CSSELR_EL1, Cache Size Selection Register, EL1
B2.33 CTR_EL0, Cache Type Register, EL0
B2.34 DCZID_EL0, Data Cache Zero ID Register, EL0
B2.35 DISR_EL1, Deferred Interrupt Status Register, EL1
B2.36 ERRIDR_EL1, Error ID Register, EL1
B2.37 ERRSELR_EL1, Error Record Select Register, EL1
B2.38 ERXADDR_EL1, Selected Error Record Address Register, EL1
B2.39 ERXCTLR_EL1, Selected Error Record Control Register, EL1
B2.40 ERXFR_EL1, Selected Error Record Feature Register, EL1
B2.41 ERXMISC0_EL1, Selected Error Record Miscellaneous Register 0, EL1
B2.42 ERXMISC1_EL1, Selected Error Record Miscellaneous Register 1, EL1
B2.43 ERXPFGCDNR_EL1, Selected Error Pseudo Fault Generation Count Down Register, EL1
B2.44 ERXPFGCTLR_EL1, Selected Error Pseudo Fault Generation Control Register, EL1
B2.45 ERXPFGFR_EL1, Selected Pseudo Fault Generation Feature Register, EL1
B2.46 ERXSTATUS_EL1, Selected Error Record Primary Status Register, EL1
B2.47 ESR_EL1, Exception Syndrome Register, EL1
B2.48 ESR_EL2, Exception Syndrome Register, EL2
B2.49 ESR_EL3, Exception Syndrome Register, EL3
B2.50 HACR_EL2, Hyp Auxiliary Configuration Register, EL2
B2.51 HCR_EL2, Hypervisor Configuration Register, EL2
B2.52 ID_AA64AFR0_EL1, AArch64 Auxiliary Feature Register 0
B2.53 ID_AA64AFR1_EL1, AArch64 Auxiliary Feature Register 1
B2.54 ID_AA64DFR0_EL1, AArch64 Debug Feature Register 0, EL1
B2.55 ID_AA64DFR1_EL1, AArch64 Debug Feature Register 1, EL1
B2.56 ID_AA64ISAR0_EL1, AArch64 Instruction Set Attribute Register 0, EL1
B2.57 ID_AA64ISAR1_EL1, AArch64 Instruction Set Attribute Register 1, EL1
B2.58 ID_AA64MMFR0_EL1, AArch64 Memory Model Feature Register 0, EL1
B2.59 ID_AA64MMFR1_EL1, AArch64 Memory Model Feature Register 1, EL1
B2.60 ID_AA64MMFR2_EL1, AArch64 Memory Model Feature Register 2, EL1
B2.61 ID_AA64PFR0_EL1, AArch64 Processor Feature Register 0, EL1
B2.62 ID_AA64PFR1_EL1, AArch64 Processor Feature Register 1, EL1
B2.63 ID_AFR0_EL1, AArch32 Auxiliary Feature Register 0, EL1
B2.64 ID_DFR0_EL1, AArch32 Debug Feature Register 0, EL1
B2.65 ID_ISAR0_EL1, AArch32 Instruction Set Attribute Register 0, EL1
B2.66 ID_ISAR1_EL1, AArch32 Instruction Set Attribute Register 1, EL1
B2.67 ID_ISAR2_EL1, AArch32 Instruction Set Attribute Register 2, EL1
B2.68 ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3, EL1
B2.69 ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4, EL1
B2.70 ID_ISAR5_EL1, AArch32 Instruction Set Attribute Register 5, EL1
B2.71 ID_ISAR6_EL1, AArch32 Instruction Set Attribute Register 6, EL1
B2.72 ID_MMFR0_EL1, AArch32 Memory Model Feature Register 0, EL1
B2.73 ID_MMFR1_EL1, AArch32 Memory Model Feature Register 1, EL1
B2.74 ID_MMFR2_EL1, AArch32 Memory Model Feature Register 2, EL1
B2.75 ID_MMFR3_EL1, AArch32 Memory Model Feature Register 3, EL1
B2.76 ID_MMFR4_EL1, AArch32 Memory Model Feature Register 4, EL1
B2.77 ID_PFR0_EL1, AArch32 Processor Feature Register 0, EL1
B2.78 ID_PFR1_EL1, AArch32 Processor Feature Register 1, EL1
B2.79 ID_PFR2_EL1, AArch32 Processor Feature Register 2, EL1
B2.80 LORC_EL1, LORegion Control Register, EL1
B2.81 LORID_EL1, LORegion ID Register, EL1
B2.82 LORN_EL1, LORegion Number Register, EL1
B2.83 MDCR_EL3, Monitor Debug Configuration Register, EL3
B2.84 MIDR_EL1, Main ID Register, EL1
B2.85 MPIDR_EL1, Multiprocessor Affinity Register, EL1
B2.86 PAR_EL1, Physical Address Register, EL1
B2.87 REVIDR_EL1, Revision ID Register, EL1
B2.88 RMR_EL3, Reset Management Register
B2.89 RVBAR_EL3, Reset Vector Base Address Register, EL3
B2.90 SCTLR_EL1, System Control Register, EL1
B2.91 SCTLR_EL2, System Control Register, EL2
B2.92 SCTLR_EL3, System Control Register, EL3
B2.93 TCR_EL1, Translation Control Register, EL1
B2.94 TCR_EL2, Translation Control Register, EL2
B2.95 TCR_EL3, Translation Control Register, EL3
B2.96 TTBR0_EL1, Translation Table Base Register 0, EL1
B2.97 TTBR0_EL2, Translation Table Base Register 0, EL2
B2.98 TTBR0_EL3, Translation Table Base Register 0, EL3
B2.99 TTBR1_EL1, Translation Table Base Register 1, EL1
B2.100 TTBR1_EL2, Translation Table Base Register 1, EL2
B2.101 VDISR_EL2, Virtual Deferred Interrupt Status Register, EL2
B2.101.1 VDISR_EL2 at EL1 using AArch64
B2.102 VSESR_EL2, Virtual SError Exception Syndrome Register
B2.103 VTCR_EL2, Virtualization Translation Control Register, EL2
B2.104 VTTBR_EL2, Virtualization Translation Table Base Register, EL2
B3 Error system registers
B3.1 Error system register summary
B3.2 ERR0ADDR, Error Record Address Register
B3.3 ERR0CTLR, Error Record Control Register
B3.4 ERR0FR, Error Record Feature Register
B3.5 ERR0MISC0, Error Record Miscellaneous Register 0
B3.6 ERR0MISC1, Error Record Miscellaneous Register 1
B3.7 ERR0PFGCDNR, Error Pseudo Fault Generation Count Down Register
B3.8 ERR0PFGCTLR, Error Pseudo Fault Generation Control Register
B3.9 ERR0PFGFR, Error Pseudo Fault Generation Feature Register
B3.10 ERR0STATUS, Error Record Primary Status Register
B4 GIC registers
B4.1 CPU interface registers
B4.2 AArch64 physical GIC CPU interface system register summary
B4.3 ICC_AP0R0_EL1, Interrupt Controller Active Priorities Group 0 Register 0, EL1
B4.4 ICC_AP1R0_EL1, Interrupt Controller Active Priorities Group 1 Register 0 EL1
B4.5 ICC_BPR0_EL1, Interrupt Controller Binary Point Register 0, EL1
B4.6 ICC_BPR1_EL1, Interrupt Controller Binary Point Register 1, EL1
B4.7 ICC_CTLR_EL1, Interrupt Controller Control Register, EL1
B4.8 ICC_CTLR_EL3, Interrupt Controller Control Register, EL3
B4.9 ICC_SRE_EL1, Interrupt Controller System Register Enable Register, EL1
B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
B4.11 ICC_SRE_EL3, Interrupt Controller System Register Enable register, EL3
B4.12 AArch64 virtual GIC CPU interface register summary
B4.13 ICV_AP0R0_EL1, Interrupt Controller Virtual Active Priorities Group 0 Register 0, EL1
B4.14 ICV_AP1R0_EL1, Interrupt Controller Virtual Active Priorities Group 1 Register 0, EL1
B4.15 ICV_BPR0_EL1, Interrupt Controller Virtual Binary Point Register 0, EL1
B4.16 ICV_BPR1_EL1, Interrupt Controller Virtual Binary Point Register 1, EL1
B4.17 ICV_CTLR_EL1, Interrupt Controller Virtual Control Register, EL1
B4.18 AArch64 virtual interface control system register summary
B4.19 ICH_AP0R0_EL2, Interrupt Controller Hyp Active Priorities Group 0 Register 0, EL2
B4.20 ICH_AP1R0_EL2, Interrupt Controller Hyp Active Priorities Group 1 Register 0, EL2
B4.21 ICH_HCR_EL2, Interrupt Controller Hyp Control Register, EL2
B4.22 ICH_VMCR_EL2, Interrupt Controller Virtual Machine Control Register, EL2
B4.23 ICH_VTR_EL2, Interrupt Controller VGIC Type Register, EL2
B5 Advanced SIMD and floating-point registers
B5.1 AArch64 register summary
B5.2 FPCR, Floating-point Control Register
B5.3 FPSR, Floating-point Status Register
B5.4 MVFR0_EL1, Media and VFP Feature Register 0, EL1
B5.5 MVFR1_EL1, Media and VFP Feature Register 1, EL1
B5.6 MVFR2_EL1, Media and VFP Feature Register 2, EL1
B5.7 AArch32 register summary
B5.8 FPSCR, Floating-Point Status and Control Register
Part C Debug descriptions
C1 Debug
C1.1 About debug methods
C1.2 Debug register interfaces
C1.2.1 Core interfaces
C1.2.2 Breakpoints and watchpoints
C1.2.3 Effects of resets on debug registers
C1.2.4 External access permissions to debug registers
C1.3 Debug events
C1.3.1 Watchpoint debug events
C1.3.2 Debug OS Lock
C1.4 External debug interface
C2 Performance Monitor Unit
C2.1 About the PMU
C2.2 PMU functional description
C2.2.1 External register access permissions
C2.3 PMU events
C2.4 PMU interrupts
C2.5 Exporting PMU events
C3 Activity Monitor Unit
C3.1 About the AMU
C3.2 Accessing the activity monitors
C3.2.1 Access enable bit
C3.2.2 System register access
C3.2.3 External memory-mapped access
C3.3 AMU counters
C3.4 AMU events
C4 Embedded Trace Macrocell
C4.1 About the ETM
C4.2 ETM trace unit generation options and resources
C4.3 ETM trace unit functional description
C4.4 Resetting the ETM
C4.5 Programming and reading ETM trace unit registers
C4.6 ETM trace unit register interfaces
C4.7 Interaction with the PMU and Debug
Part D Debug registers
D1 AArch32 debug registers
D1.1 AArch32 debug register summary
D2 AArch64 debug registers
D2.1 AArch64 debug register summary
D2.2 DBGBCRn_EL1, Debug Breakpoint Control Registers, EL1
D2.3 DBGCLAIMSET_EL1, Debug Claim Tag Set Register, EL1
D2.4 DBGWCRn_EL1, Debug Watchpoint Control Registers, EL1
D3 Memory-mapped debug registers
D3.1 Memory-mapped debug register summary
D3.2 EDCIDR0, External Debug Component Identification Register 0
D3.3 EDCIDR1, External Debug Component Identification Register 1
D3.4 EDCIDR2, External Debug Component Identification Register 2
D3.5 EDCIDR3, External Debug Component Identification Register 3
D3.6 EDDEVID, External Debug Device ID Register 0
D3.7 EDDEVID1, External Debug Device ID Register 1
D3.8 EDPIDR0, External Debug Peripheral Identification Register 0
D3.9 EDPIDR1, External Debug Peripheral Identification Register 1
D3.10 EDPIDR2, External Debug Peripheral Identification Register 2
D3.11 EDPIDR3, External Debug Peripheral Identification Register 3
D3.12 EDPIDR4, External Debug Peripheral Identification Register 4
D3.13 EDPIDRn, External Debug Peripheral Identification Registers 5-7
D3.14 EDRCR, External Debug Reserve Control Register
D4 AArch32 PMU registers
D4.1 AArch32 PMU register summary
D4.2 PMCEID0, Performance Monitors Common Event Identification Register 0
D4.3 PMCEID1, Performance Monitors Common Event Identification Register 1
D4.4 PMCR, Performance Monitors Control Register
D5 AArch64 PMU registers
D5.1 AArch64 PMU register summary
D5.2 PMCEID0_EL0, Performance Monitors Common Event Identification Register 0, EL0
D5.3 PMCEID1_EL0, Performance Monitors Common Event Identification Register 1, EL0
D5.4 PMCR_EL0, Performance Monitors Control Register, EL0
D6 Memory-mapped PMU registers
D6.1 Memory-mapped PMU register summary
D6.2 PMCFGR, Performance Monitors Configuration Register
D6.3 PMCIDR0, Performance Monitors Component Identification Register 0
D6.4 PMCIDR1, Performance Monitors Component Identification Register 1
D6.5 PMCIDR2, Performance Monitors Component Identification Register 2
D6.6 PMCIDR3, Performance Monitors Component Identification Register 3
D6.7 PMPIDR0, Performance Monitors Peripheral Identification Register 0
D6.8 PMPIDR1, Performance Monitors Peripheral Identification Register 1
D6.9 PMPIDR2, Performance Monitors Peripheral Identification Register 2
D6.10 PMPIDR3, Performance Monitors Peripheral Identification Register 3
D6.11 PMPIDR4, Performance Monitors Peripheral Identification Register 4
D6.12 PMPIDRn, Performance Monitors Peripheral Identification Register 5-7
D7 PMU snapshot registers
D7.1 PMU snapshot register summary
D7.2 PMPCSSR, Snapshot Program Counter Sample Register
D7.3 PMCIDSSR, Snapshot CONTEXTIDR_EL1 Sample Register
D7.4 PMCID2SSR, Snapshot CONTEXTIDR_EL2 Sample Register
D7.5 PMSSSR, PMU Snapshot Status Register
D7.6 PMOVSSR, PMU Overflow Status Snapshot Register
D7.7 PMCCNTSR, PMU Cycle Counter Snapshot Register
D7.8 PMEVCNTSRn, PMU Cycle Counter Snapshot Registers 0-5
D7.9 PMSSCR, PMU Snapshot Capture Register
D8 AArch64 AMU registers
D8.1 AArch64 AMU register summary
D8.2 AMCNTENCLR0_EL0, Activity Monitors Count Enable Clear Register, EL0
D8.3 AMCNTENSET_EL0, Activity Monitors Count Enable Set Register, EL0
D8.4 AMCFGR_EL0, Activity Monitors Configuration Register, EL0
D8.5 AMUSERENR_EL0, Activity Monitor EL0 Enable access, EL0
D8.6 AMEVCNTRn_EL0, Activity Monitor Event Counter Register, EL0
D8.7 AMEVTYPERn_EL0, Activity Monitor Event Type Register, EL0
D9 ETM registers
D9.1 ETM register summary
D9.2 TRCACATRn, Address Comparator Access Type Registers 0-7
D9.3 TRCACVRn, Address Comparator Value Registers 0-7
D9.4 TRCAUTHSTATUS, Authentication Status Register
D9.5 TRCAUXCTLR, Auxiliary Control Register
D9.6 TRCBBCTLR, Branch Broadcast Control Register
D9.7 TRCCCCTLR, Cycle Count Control Register
D9.8 TRCCIDCCTLR0, Context ID Comparator Control Register 0
D9.9 TRCCIDCVR0, Context ID Comparator Value Register 0
D9.10 TRCCIDR0, ETM Component Identification Register 0
D9.11 TRCCIDR1, ETM Component Identification Register 1
D9.12 TRCCIDR2, ETM Component Identification Register 2
D9.13 TRCCIDR3, ETM Component Identification Register 3
D9.14 TRCCLAIMCLR, Claim Tag Clear Register
D9.15 TRCCLAIMSET, Claim Tag Set Register
D9.16 TRCCNTCTLR0, Counter Control Register 0
D9.17 TRCCNTCTLR1, Counter Control Register 1
D9.18 TRCCNTRLDVRn, Counter Reload Value Registers 0-1
D9.19 TRCCNTVRn, Counter Value Registers 0-1
D9.20 TRCCONFIGR, Trace Configuration Register
D9.21 TRCDEVAFF0, Device Affinity Register 0
D9.22 TRCDEVAFF1, Device Affinity Register 1
D9.23 TRCDEVARCH, Device Architecture Register
D9.24 TRCDEVID, Device ID Register
D9.25 TRCDEVTYPE, Device Type Register
D9.26 TRCEVENTCTL0R, Event Control 0 Register
D9.27 TRCEVENTCTL1R, Event Control 1 Register
D9.28 TRCEXTINSELR, External Input Select Register
D9.29 TRCIDR0, ID Register 0
D9.30 TRCIDR1, ID Register 1
D9.31 TRCIDR2, ID Register 2
D9.32 TRCIDR3, ID Register 3
D9.33 TRCIDR4, ID Register 4
D9.34 TRCIDR5, ID Register 5
D9.35 TRCIDR8, ID Register 8
D9.36 TRCIDR9, ID Register 9
D9.37 TRCIDR10, ID Register 10
D9.38 TRCIDR11, ID Register 11
D9.39 TRCIDR12, ID Register 12
D9.40 TRCIDR13, ID Register 13
D9.41 TRCIMSPEC0, Implementation Specific Register 0
D9.42 TRCITATBIDR, Integration ATB Identification Register
D9.43 TRCITCTRL, Integration Mode Control Register
D9.44 TRCITIATBINR, Integration Instruction ATB In Register
D9.45 TRCITIATBOUTR, Integration Instruction ATB Out Register
D9.46 TRCITIDATAR, Integration Instruction ATB Data Register
D9.47 TRCLAR, Software Lock Access Register
D9.48 TRCLSR, Software Lock Status Register
D9.49 TRCCNTVRn, Counter Value Registers 0-1
D9.50 TRCOSLAR, OS Lock Access Register
D9.51 TRCOSLSR, OS Lock Status Register
D9.52 TRCPDCR, Power Down Control Register
D9.53 TRCPDSR, Power Down Status Register
D9.54 TRCPIDR0, ETM Peripheral Identification Register 0
D9.55 TRCPIDR1, ETM Peripheral Identification Register 1
D9.56 TRCPIDR2, ETM Peripheral Identification Register 2
D9.57 TRCPIDR3, ETM Peripheral Identification Register 3
D9.58 TRCPIDR4, ETM Peripheral Identification Register 4
D9.59 TRCPIDRn, ETM Peripheral Identification Registers 5-7
D9.60 TRCPRGCTLR, Programming Control Register
D9.61 TRCRSCTLRn, Resource Selection Control Registers 2-16
D9.62 TRCSEQEVRn, Sequencer State Transition Control Registers 0-2
D9.63 TRCSEQRSTEVR, Sequencer Reset Control Register
D9.64 TRCSEQSTR, Sequencer State Register
D9.65 TRCSSCCR0, Single-Shot Comparator Control Register 0
D9.66 TRCSSCSR0, Single-Shot Comparator Status Register 0
D9.67 TRCSTALLCTLR, Stall Control Register
D9.68 TRCSTATR, Status Register
D9.69 TRCSYNCPR, Synchronization Period Register
D9.70 TRCTRACEIDR, Trace ID Register
D9.71 TRCTSCTLR, Global Timestamp Control Register
D9.72 TRCVICTLR, ViewInst Main Control Register
D9.73 TRCVIIECTLR, ViewInst Include-Exclude Control Register
D9.74 TRCVISSCTLR, ViewInst Start-Stop Control Register
D9.75 TRCVMIDCVR0, VMID Comparator Value Register 0
D9.76 TRCVMIDCCTLR0, Virtual context identifier Comparator Control Register 0
Part E Appendices
A Cortex®‑A76 Core AArch32 unpredictable behaviors
A.1 Use of R15 by Instruction
A.2 Load/Store accesses crossing page boundaries
A.3 Armv8 Debug UNPREDICTABLE behaviors
A.4 Other UNPREDICTABLE behaviors
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-00 9 December 2016 Confidential First draft for r0p0
0000-01 26 May 2017 Confidential First release for r0p0
0100-00 20 October 2017 Confidential First release for r1p0
0200-00 13 April 2018 Confidential First release for r2p0
0300-00 27 July 2018 Non-Confidential First release for r3p0

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